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Pull requests: lnis-uofu/OpenFPGA

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Pull requests list

Bump yosys from 7d3819c to 4821ed1 dependencies Pull requests that update a dependency file submodules Pull requests that update Submodules code
#2667 opened Jul 29, 2026 by dependabot Bot Loading…
Bump vtr-verilog-to-routing from bebb46c to a3e60c3 dependencies Pull requests that update a dependency file submodules Pull requests that update Submodules code
#2666 opened Jul 29, 2026 by dependabot Bot Loading…
[WIP] add WASI build github
#2519 opened May 13, 2026 by tangxifan Collaborator Loading…
[WIP] VPR command intergration build documentation flow-scripts lang-make openfpga-tools VPR
#2473 opened Apr 24, 2026 by ganeshgore Collaborator • Draft
[WIP] Remapping Bitstream architecture-description documentation flow-scripts openfpga-bitstream openfpga-tools tests
#2414 opened Mar 6, 2026 by ganeshgore Collaborator • Draft
@amin1377
2
[fabric_bitstream] Adding custom bitstream remap openfpga-bitstream openfpga-tools
#2022 opened Jun 4, 2025 by amin1377 Collaborator Loading…
4
Use hierarchical block names openfpga-tools VPR wontfix This will not be worked on
#1976 opened Apr 7, 2025 by amin1377 Collaborator Loading…
Add command to generate repack design constraints openfpga-tools
#1889 opened Nov 6, 2024 by fkosar-ql Collaborator • Draft
@amin1377
8
Make sure net is valid before setting it as wire LUT output openfpga-tools
#1719 opened Jun 19, 2024 by chungshien Collaborator Loading…
7
Preserve escaped names openfpga-tools openfpga-verilog
#1589 opened Mar 4, 2024 by alaindargelas Loading…
3
Update FindTBB.cmake
#1238 opened Jun 27, 2023 by yppah56 Loading…
Update FindTBB.cmake
#1161 opened May 10, 2023 by zaidtahirbutt Loading…
2
Relative paths in run_modelsim.py and other changes to make Modelsim work on non-Utah machines architecture-description flow-scripts
#247 opened Feb 20, 2021 by nachiket Contributor Loading…
3 of 16 tasks
9
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