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feat(M4-P0C1): ESP32-P4 three-SV binary staging, atomic commit and readback - #336
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…hout TX activation
…plane without enabling multi TX
…plane without enabling multi TX
…plane without enabling multi TX
…n, CRC rejection and atomic readback
… semantics and next TX milestone
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M4-P0C1 — ESP32-P4 control-plane implementation for three SCL-derived SV profiles
Part of M4 issue #333 and ARD. Builds on merged P0A/P0B.
Implemented in firmware
MultiSvConfigStorewith exactly three nested V1 device profiles inside the already mergedARM3 V2codec. No XML parser, heap allocation, new RT task, or 3 copies of the PTP clock.MULTISV BEGIN/CHUNK/VALIDATE/COMMIT/ABORT/STATUS/SHOWUART command family (existing 192-byte command bound; 48-byte binary chunks, sequential offsets, monotonic transactions).candidate_andcommitted_profiles_banks; commit is all-or-nothing and preserves previous committed roster on any corrupt/partial upload.arstack_process_buscomponent; new control handler linked into the main IDF component and dispatched from existing UART control loop.configured,generation, full-envelopehash,bytes, 3 MAC/APPID/svID/VLAN/rate identities.MULTISV-CONFIG-STAGING-V2; command responses explicitly sayoutput=INACTIVE_UNTIL_M4_P0C2. LegacyPROFILE V1START and single-SV TX remain unchanged.Gate / what is not in this PR
This PR commits the firmware control-plane roster, NOT the actual three-stream TX engine. Do not advertise
SV-MULTI3-V1yet. The shared PTP grid/publisher task, three isolated waveform banks and GUI pages belong to subsequent P0C2/P0D/P0E.CI required: C++ GCC+Clang+MSVC, ESP32-P4 firmware build, Embedded Profile, Studio Qt regressions. No change to published official M3.H.3 binaries. Protocol contract.