A basic CPU architecture designed in Quartus as part of a Computer Architecture course project.
This project was developed for the Computer Architecture course using Intel Quartus II.
The objective was to design and implement the core components of an educational CPU based on the project specifications provided in the course.
The implemented system includes:
- Arithmetic Logic Unit (ALU)
- Control Unit
- Program Counter (PC)
- Address Register (AR)
- Data Register (DR)
- Accumulator (AC)
- Instruction Register (IR)
- Input Register (INPR)
- Memory interface
- Instruction decoding and execution logic
/Components: Contains the individual design blocks (AC, AR, DR, IR, Memory, etc.)./Project: Contains the main Quartus project files (.bdf,.qpf,.qsf)./Documentation: Contains detailed project documentation (PDF) and design screenshots.
This project was completed according to the academic requirements of the course. It is intended as an educational CPU implementation rather than a complete commercial processor. Some advanced architectural features were outside the scope of the assignment.
The image below shows the overall CPU design implemented in Quartus II, including the main components and their connections.
