Rewrite tx NEON kernels with native intrinsics and remove sse2neon.h - #167
Merged
Conversation
Signed-off-by: KP Choi <kp5.choi@samsung.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
xeve_tq_neon.cwas the AVX2 kernel run through an in-file AVX emulation layeron top of the bundled
sse2neon.h. This rewrites the four transform kernels(8/16/32/64) with native NEON intrinsics and removes
sse2neon.hentirely —it was only included by this one file (the other NEON kernels are already
native). Follow-up to the sse2neon concern raised in #161.
The second pass accumulates coefficient products in 64 bits, matching the C
version's dynamic range (the first pass is called with shift 0).
Verified with an aarch64 cross build under qemu: bit-exact bitstreams against
the x86 build across noise/flat/gradient inputs, both profiles, multiple QPs,
single- and multi-threaded, plus a function-level test against the C kernels
(sizes 8-64, lines 1-128, both steps, realistic value ranges). Real-hardware
performance numbers are welcome.