lab: Milestone 2 — SYT realism: TxTimingModel, simulated timeline, P5 verification (stacked on #24)#25
Merged
Conversation
… verification
Implements the M2 scope per the lab README, with every constant taken from
the DICE tree's Saffire-decompile ground truth (SYTGenerator.hpp,
TxOutputPhaseLoop.hpp, tools/debug/tx_phase_loop_model.py):
- Ports/ICycleTimeline: time as an explicit port (unwrapped 24.576 MHz
ticks). Lab/SimulatedCycleTimeline synthesizes it from audio frame
position (6 frames per cycle at 48 kHz; epoch + jitter knobs are test
inputs, per the README's adversarial-schedule design).
- Core/TxTimingModel: the frame->cycle->SYT unit under research. Seeds at
now + presentation delay (4096), grafts the device's constant sub-cycle
(phase - phase%3072 + 0x0B0, the reference-model formula), advances by
the fixed 4096-tick blocking step in the 16-cycle (49152) SYT domain,
and reports transmit-lead health: tight <=3071, accept <7620 (the real
rejection threshold), gate >=7620, escalate >=12287 (advisory only).
WHO DECIDES THE WIRE: not the model — cadence stays authoritative;
callers Peek the SYT, the packetizer decides data/no-data, and only
emitted data packets Commit (the model tracks, it never decides),
mirroring TxOutputPhaseLoop's contract.
- Verifier P5 (config-gated): data SYTs must step by exactly 4096 in the
16-cycle domain and sit on the graft lattice (offset = 0x0B0 mod 1024);
data packets carrying 0xFFFF in a timing-valid run are violations.
Self-tests prove each P5 counter fires exactly once per injected fault.
- Controller: EnableLabTiming/PrepareLabPacketTimed/TimingCounters — the
timed prepare path peeks, prepares, commits-on-data, and records lead
health telemetry (seeds counted at peek: the seeding peek can land on a
no-data cycle).
- Lab/WriteEndTraceReplayer: allocation-free trace-text parser
(sample_time host_time frames; comments; malformed lines counted, never
absorbed) + Replay — the regression harness Milestone 3's captured
trace will drop into. Scenario H replays a trace through the full
timed pipeline.
- Dext wiring: timing + P5 enabled in VirtualAudioDevice; the simulated
bus rides the exposure cursor (the packet's projected transmit
position, per Saffire FillFirewireBuffers); StopIO dump grows p5 and
timing lines.
Unit tests pin the contract exactly: seed SYT 0x10B0 at lead 3248, the
+1,+1,+2 cycle pattern with offsets {0x0B0,0x4B0,0x8B0}, the 12-packet
16-cycle wrap, all five lead-health boundaries, graft-disabled mode, the
monotonic guard, and re-arm/reseed. The timed pump soak holds P1-P5 at
zero violations with the lead pinned at the seed value across ~65k data
packets.
Suite: 18010 checks, 0 failures (was 17440). All three targets build.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
mrmidi
added a commit
that referenced
this pull request
Jun 12, 2026
lab: Milestone 2 — SYT realism: TxTimingModel, simulated timeline, P5 verification (stacked on #24)
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
What
Milestone 2 per the lab README — SYT realism, the piece you flagged as important for testing ZTS and SYT behavior. Stacked on #24 (M3 bring-up); review the top commit.
Every constant comes from your Saffire-decompile ground truth (
SYTGenerator.hpp,TxOutputPhaseLoop.hpp,tools/debug/tx_phase_loop_model.py) — nothing re-derived.The pieces
Ports/ICycleTimeline— time as an explicit port (unwrapped 24.576 MHz ticks).Lab/SimulatedCycleTimelinesynthesizes it from audio frame position (6 frames/cycle at 48 kHz); epoch + jitter are constructor/test inputs per the README's adversarial-schedule design.Core/TxTimingModel— the frame→cycle→SYT unit under research:phase − phase%3072 + 0x0B0(your reference model's exact formula)+1,+1,+2cycle pattern with offsets{0x0B0, 0x4B0, 0x8B0}TxOutputPhaseLoop's contract).Lab/WriteEndTraceReplayer— allocation-free trace-text parser + replay (malformed lines counted, never absorbed); scenario H replays a recorded WriteEnd sequence through the full timed pipeline — the regression harness the M3-captured trace will drop into.FillFirewireBuffers) so lead sits at the grafted seed by construction;StopIOdump growsp5_step/p5_graftand atiming:line.Verification
Unit tests pin the contract exactly: seed SYT
0x10B0at lead 3248; the 12-packet/16-cycle wrap; all five lead-health boundaries at their exact tick values (3071/3072/7619/7620/12286/12287); graft-disabled mode; the monotonic guard; re-arm/reseed. The timed pump soak holds P1–P5 at zero violations with the lead pinned at the seed across ~65k data packets. All three targets build.🤖 Generated with Claude Code