FROMLIST: arm64: dts: qcom: qcs6490: Enable DP and HDMI audio out for kodiak#970
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ks5-dev wants to merge 21 commits intoqualcomm-linux:tech/all/dt/qcs6490from
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FROMLIST: arm64: dts: qcom: qcs6490: Enable DP and HDMI audio out for kodiak#970ks5-dev wants to merge 21 commits intoqualcomm-linux:tech/all/dt/qcs6490from
ks5-dev wants to merge 21 commits intoqualcomm-linux:tech/all/dt/qcs6490from
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Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-6-46e085bca4cc@oss.qualcomm.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
Add support for SYSTEM_RESET2 vendor-specific resets in qcm6490-idp as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-8-46e085bca4cc@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
…ypes Add support for SYSTEM_RESET2 vendor-specific resets in qcs6490-rb3gen2 as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-9-46e085bca4cc@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
…e configuration The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform but has a different thermal junction temperature specification due to package-level differences. Update passive/hot trip thresholds to 105°C and critical trip thresholds to 115°C for various subsystem TSENS sensors. Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation is handled automatically in hardware on this board. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215105934.2428987-1-manaf.pallikunhi@oss.qualcomm.com
Enable cdsp cooling devices and cooling map bindings for cdsp. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251223123227.1317244-8-gaurav.kohli@oss.qualcomm.com
…2 industrial mezzanine
Below is the routing diagram of dsi lanes from qcs6490 soc to
mezzanine.
DSI0 --> SW1403.4 --> LT9611uxc --> hdmi port
|
--> SW2700.1 --> dsi connector
|
--> LT9211c --> LVDS connector
Disable hdmi connector for industrial mezzanine and enable
LT9211c bridge and lvds panel node.
LT9211c is powered by default with reset gpio connected to 117.
Link: https://lore.kernel.org/r/20260130-add-lt9211c-bridge-for-rb3gen2-industrial-mezzanine-v2-1-a98714fa1531@oss.qualcomm.com
Signed-off-by: Gopi Botlagunta <venkata.botlagunta@oss.qualcomm.com>
Co-developed-by: Yi Zhang <zhanyi@qti.qualcomm.com>
Signed-off-by: Yi Zhang <zhanyi@qti.qualcomm.com>
Add the PMU node for WCN6750 present on the qcm6490-idp board and assign its power outputs to the Bluetooth module. In WCN6750 module sw_ctrl and wifi-enable pins are handled in the wifi controller firmware. Therefore, it is not required to have those pins' entries in the PMU node. Link: https://lore.kernel.org/r/20260203071807.764036-1-janaki.thota@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Janaki Ramaiah Thota <janaki.thota@oss.qualcomm.com>
Remove PCIe1 clocks from protected-list and enable PCIe1 controller and its corresponding PHY nodes on qcm6490-idp platform. PCIe1 is used to connect NVMe based SSD's on this platform. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260212-qcm6490-idp-v1-1-80a45bd46ac5@oss.qualcomm.com
GCC_PCIE_CLKREF_EN controls a repeater that provides the reference clock only to the PCIe0 PHY. PCIe1 PHY receives its refclk directly from the CXO source. If the PCIe1 driver in HLOS votes for or against GCC_PCIE_CLKREF_EN, it will inadvertently modify the refclk to PCIe0 as well. Since PCIe0 is managed by WPSS while PCIe1 is managed in HLOS, there is no mechanism to coordinate these votes. As a result, HLOS may disable this repeater during suspend and cut off the PCIe0 PHY refclk while PCIe0 is still active. Replace the unused GCC_PCIE_CLKREF_EN clock entry with RPMH_CXO_CLK to reflect the actual hardware wiring and prevent unintended changes to PCIe0 clocking. Fixes: 92e0ee9 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Cc: stable@vger.kernel.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260123-fix_pcie1_phy_clk-v1-1-38f82ea01792@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
The WCD9370 audio codec reset line on QCM6490 IDP should be active-low, but the device tree described it as active-high. As a result, the codec is kept in reset and fails to reset the SoundWire, leading to timeouts and ASoC card probe failure (-ETIMEDOUT). Fix the reset GPIO polarity to GPIO_ACTIVE_LOW so the codec can properly initialize. Link: https://lore.kernel.org/all/20260220090220.2992193-1-ravi.hothi@oss.qualcomm.com/ Fixes: aa04c29 ("arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec") Signed-off-by: Ravi Hothi <ravi.hothi@oss.qualcomm.com>
… HPD The base device tree configures the edp_hot_plug_det pin using the "edp_hot" function on GPIO 60. However, on qcs6490-rb3gen2 this external HPD GPIO does not generate a connect event when a display is already connected at boot, causing the DP/eDP display to remain disabled. The DP controller’s native HPD correctly detects the connected sink in this scenario, so continue using the DP controller native HPD on the qcs6490-rb3gen2 platform instead of the external HPD GPIO. Link: https://lore.kernel.org/all/20260228-edp_hpd_rb3_gen2_for_next-v1-1-aebc047eddc1@oss.qualcomm.com/ Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
… TC9563 PCIe switch node for PCIe0 Add a node for the TC9563 PCIe switch connected to PCIe0. The switch has three downstream ports.Two embedded Ethernet devices are present on one of the downstream ports. All the ports present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, which are on by default and are added as fixed regulators. TC9563 can be configured through I2C. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260212-industrial-mezzanine-pcie-v3-1-1e152937a76a@oss.qualcomm.com/
… second TC9563 PCIe switch node for PCIe1 Add a node for the second TC9563 PCIe switch on PCIe1, which is connected in cascade to the first TC9563 switch via the former's downstream port. Two embedded Ethernet devices are present on one of the downstream ports of this second switch as well. All the ports present in the node represent the downstream ports and embedded endpoints. The second TC9563 is powered up via the same LDO regulators as the first one, and these can be controlled via two GPIOs, which are already present as fixed regulators. This TC9563 can also be configured through I2C. Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260212-industrial-mezzanine-pcie-v3-2-1e152937a76a@oss.qualcomm.com/
… nodes The MCP251XFD can expose two pins as GPIOs. The binding already declares gpio-controller and #gpio-cells for the device. Whitelist GPIO hog child nodes using patternProperties so boards can set default GPIO states at boot via DT, consistent with other GPIO controllers (e.g. microchip,mpfs-gpio). Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260108125200.2803112-2-viken.dadhaniya@oss.qualcomm.com/
Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform. The controller is connected via SPI3 and uses a 40 MHz oscillator. A GPIO hog for GPIO0 is included to configure the CAN transceiver in Normal mode during boot. Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260108125200.2803112-3-viken.dadhaniya@oss.qualcomm.com/
This reverts commit 776fe08. Update trip threshold back to 95 degree as 105 is not applicable for all rb3gen2 boards. So reverting this change. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
Enable Qualcomm BCL hardware devicetree binding configuration for pm8350c. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-4-7b426f0b77a1@oss.qualcomm.com
Enable Qualcomm BCL hardware devicetree binding configuration for pm7250b. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260206-qcom-bcl-hwmon-v1-3-7b426f0b77a1@oss.qualcomm.com
All the existing variants Kodiak boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Kodiak IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Link: https://lore.kernel.org/lkml/20260327131043.627120-2-sumit.garg@kernel.org/ Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> [SG: watchdog fixup] Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> [Mukesh: Added support for more variants] Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
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CRs-Fixed: 4502072
dont add to commit log. Adding in PR description is sufficient.
Enable secondary mi2s to support HDMI audio. Link: https://lore.kernel.org/all/20260413091937.134469-2-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
Add new dai link to enable DP audio. Link: https://lore.kernel.org/all/20260413091937.134469-3-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
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This series adds the dt and driver changes for enabling
audio over HDMI and Displayport on Kodiak.
CRs-Fixed: 4502072
Link:
https://lore.kernel.org/all/20260413091937.134469-2-kumar.singh@oss.qualcomm.com/
https://lore.kernel.org/all/20260413091937.134469-3-kumar.singh@oss.qualcomm.com/