Prepare qcom-next based on tag 'Linux 7.1-rc2' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#545
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…extended CTI Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Numbered sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI. On Qualcomm CTIs, only banked registers backed by hardware are exposed, with the number of visible banks derived from nr_trig_max. This ensures that userspace only sees registers that are actually implemented, while maintaining compatibility with existing CTI tooling. Link: https://lore.kernel.org/linux-arm-msm/20260426-extended-cti-v8-4-23b900a4902f@oss.qualcomm.com/ Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
Add MIPI OST(Open System Trace) protocol support for stm to format the traces. The OST Protocol abstracts the underlying layers from the sending and receiving applications, thus removing dependencies on the connection media and platform implementation. OST over STP packet consists of Header/Payload/End. Header is designed to include the information required by all OST packets. Information that is not shared by all packets is left to the higher layer protocols. Thus, the OST Protocol Header can be regarded as the first part of a complete OST Packet Header, while a higher layer header can be regarded as an extension designed for a specific purpose. +--------+--------+--------+--------+ | start |version |entity |protocol| +--------+--------+--------+--------+ | stm version | magic | +-----------------------------------+ | cpu | +-----------------------------------+ | timestamp | | | +-----------------------------------+ | tgid | | | +-----------------------------------+ | payload | +-----------------------------------+ | ... | end | +-----------------------------------+ In header, there will be STARTSIMPLE/VERSION/ENTITY/PROTOCOL. STARTSIMPLE is used to signal the beginning of a simplified OST protocol. The Version field is a one byte, unsigned number identifying the version of the OST Protocol. The Entity ID field is a one byte unsigned number that identifies the source. The Protocol ID field is a one byte unsigned number identifying the higher layer protocol of the OST Packet, i.e. identifying the format of the data after the OST Protocol Header. OST Control Protocol ID value represents the common control protocol, the remaining Protocol ID values may be used by any higher layer protocols capable of being transported by the OST Protocol. Link: https://lore.kernel.org/all/20260129-p_ost-v5-1-2b14fff39428@oss.qualcomm.com/ Co-developed-by: Tingwei Zhang <tingwei.zhang@oss.qualcomm.com> Signed-off-by: Tingwei Zhang <tingwei.zhang@oss.qualcomm.com> Co-developed-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com> Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com> Co-developed-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
…' property Introduce the `qcom,cpu-bound-components` boolean property for CoreSight components (TMC, Funnel, and Replicator). This property indicates that the component is physically located within a CPU cluster power domain. Such components share the power state of the cluster and may require special handling (e.g., cross-CPU register access) compared to system-wide components. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-1-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Funnels associated with CPU clusters reside in the cluster's power domain.
Unlike dynamic funnels (which are typically system-wide), these per-cluster
funnels are only accessible when the cluster is powered on. Standard
runtime PM may not suffice to wake up a cluster from low-power states,
making direct register access unreliable.
Enhance the funnel driver to support these per-cluster devices:
1. Safe Initialization:
- Identify CPU cluster funnels via "qcom,cpu-bound-components".
- Use smp_call_function_single() to perform hardware initialization
(claim tag clearing) on a CPU within the cluster.
- Refactor the probe flow to encapsulate device registration in
funnel_add_coresight_dev().
2. Cross-CPU Enablement:
- Update funnel_enable() to use smp_call_function_single() when
enabling the hardware on a cluster-bound funnel.
3. Debug Interface Support:
- Update funnel_ctrl_show() to safely read the control register via
cross-CPU calls when necessary.
This ensures that funnel operations remain safe and functional even when
the associated CPU cluster is in aggressive low-power states.
Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-2-2335a6ae62a0@oss.qualcomm.com/
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Per-cluster funnels rely on the associated CPU cluster being online to securely access registers during initialization. If all CPUs in the cluster are offline during probe, these operations fail. Support deferred initialization for these devices: 1. Track funnels that fail to probe due to offline CPUs in a global list. 2. Register a CPU hotplug notifier (funnel_online_cpu) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration with the CoreSight framework. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-3-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
…lization
Replicators associated with CPU clusters reside in the cluster's power
domain. Unlike system-wide replicators, their registers are only
accessible when the cluster is powered on. Standard runtime PM may not
suffice to wake up a cluster from low-power states, making direct
register access unreliable during initialization or operation.
Enhance the replicator driver to support these per-cluster devices:
1. Safe Initialization:
- Identify per-cluster replicators via device properties.
- Use smp_call_function_single() to perform hardware initialization
(reset and claim tag clearing) on a CPU within the cluster.
- Refactor the probe flow to encapsulate device registration in
replicator_add_coresight_dev().
2. Cross-CPU Enablement:
- Update replicator_enable() to use smp_call_function_single()
when enabling the hardware on a cluster-bound replicator.
3. Claim/Disclaim Handling:
- Introduce replicator_claim/disclaim_device_unlocked() to manage
device access safely before full framework registration.
This ensures that replicator operations remain robust even when the
associated CPU cluster is in low-power states, while maintaining
compatibility with existing system-level replicators.
Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-4-2335a6ae62a0@oss.qualcomm.com/
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
…offline Per-cluster replicators rely on the associated CPU cluster being online to securely access registers during initialization. If all CPUs in the cluster are offline during probe, these operations fail. Support deferred initialization for these devices: 1. Track replicators that fail to probe due to offline CPUs in a global list. 2. Register a CPU hotplug notifier (`replicator_online_cpu`) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration with the CoreSight framework. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-5-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
…ound devices Standard system replicators allow direct register access from any CPU. However, replicators associated with specific CPU clusters share the cluster's power domain and require access via a CPU within that domain. Replace the standard `coresight_simple_reg*` accessors with custom handlers (`coresight_replicator_reg*`) to support these devices: - For cluster-bound replicators (indicated by `supported_cpus`), use `smp_call_function_single()` to read registers on an associated CPU. - For standard replicators, retain the direct access behavior. This ensures correct operation for per-cluster replicators while maintaining compatibility for existing system-level devices. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-6-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
…ster TMCs TMC instances associated with CPU clusters reside in the cluster's power domain. Unlike system-level TMCs, their registers are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states during probe, making direct register access unreliable. Refactor the probe sequence to handle these per-cluster devices safely: 1. Identify per-cluster TMCs using the "qcom,cpu-bound-components" property. 2. For such devices, use `smp_call_function_single()` to perform hardware initialization (`tmc_init_hw_config`) on a CPU within the cluster. This ensures the domain is powered during access. 3. Factor out the device registration logic into `tmc_add_coresight_dev()`. This allows common registration code to be shared between the standard probe path and the deferred probe path (used when the associated CPUs are initially offline). This change ensures reliable initialization for per-cluster TMCs while maintaining backward compatibility for standard system-level TMCs. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-7-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
… ETF support
TMC-ETF devices associated with specific CPU clusters share the cluster's
power domain. Accessing their registers requires the cluster to be powered
on, which can only be guaranteed by running code on a CPU within that
cluster.
Refactor the enablement logic to support this requirement:
1. Split `tmc_etf_enable_hw` and `tmc_etb_enable_hw` into local and
SMP-aware variants:
- `*_local`: Performs the actual register access.
- `*_smp_call`: Wrapper for `smp_call_function_single`.
- The main entry point now detects if the device is CPU-bound and uses
`smp_call_function_single` to execute the local variant on an
appropriate CPU if necessary.
2. Adjust locking in `tmc_enable_etf_sink_sysfs` and `tmc_enable_etf_link`:
- Drop the spinlock before calling `tmc_etf_enable_hw`. This is
necessary because `smp_call_function_single` (used for cross-CPU
calls) may require interrupts enabled or might sleep/wait, which is
unsafe under a spinlock.
- Re-acquire the lock afterwards to update driver state.
Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-8-2335a6ae62a0@oss.qualcomm.com/
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
The current TMC management interface (sysfs attributes) assumes that device registers can be accessed directly from any CPU. However, for TMCs associated with specific CPU clusters, registers must be accessed from a CPU within that cluster. Replace the standard `coresight_simple_reg*` handlers with custom accessors (`coresight_tmc_reg*`). These new handlers check if the TMC is bound to a specific set of CPUs: - If bound, they use `smp_call_function_single()` to read the register on an appropriate CPU. - If not bound (global TMC), they fall back to direct access. This ensures correct register reads for per-cluster TMC devices while maintaining backward compatibility for global TMCs. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-9-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
On some platforms, the TMC driver may probe before the associated CPUs are online. This prevents the driver from securely accessing the hardware or configuring it via smp_call_function_single(), which requires the target CPU to be available. To address this, defer the hardware initialization if the associated CPUs are offline: 1. Track such deferred devices in a global list. 2. Register a CPU hotplug callback (`tmc_online_cpu`) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration for the waiting TMC devices. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-10-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Currently, the link enable callback does not receive the CoreSight mode (enum cs_mode). This prevents link drivers from knowing whether they are being enabled for SysFS or Perf. This distinction is crucial because Perf mode runs in atomic context, where certain operations (like smp_call_function_single()) are unsafe. Without knowing the mode, drivers cannot conditionally avoid these unsafe calls. Update the `enable` callback in `struct coresight_ops_link` to accept `enum cs_mode`. This allows drivers to implement mode-specific logic, such as using atomic-safe enablement sequences when running in Perf mode. Update all call sites and driver implementations accordingly. Link: https://lore.kernel.org/all/20251218-cpu_cluster_component_pm-v2-11-2335a6ae62a0@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Document the platforms that fallback to using the qcom,sa8775p-ctcu compatible for probing. Link: https://lore.kernel.org/all/20260204-enable-ctcu-and-etr-v3-1-0bb95c590ae1@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…ersion matches Since USB can disconnect at any time, if it disconnects during the BT firmware download, the BT controller firmware version may still be updated even without completing the download. When USB reconnects, the BT host detects the same version as in the firmware file, which prevents the firmware from being downloaded again. Therefore, remove the equality check to ensure that after USB reconnection, the BT host can still download the firmware. Signed-off-by: Shuai Zhang <shuai.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260108074353.1027877-1-shuai.zhang@oss.qualcomm.com/
…for ice node Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for it's own resources. Before accessing ICE hardware, the 'core' and 'iface' clocks must be turned on by the driver. This can only be done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the GCC_UFS_PHY_GDSC power domain and 'core' and 'iface' clocks in the ICE node for kaanapali. Link: https://lore.kernel.org/all/20260123-qcom_ice_power_and_clk_vote-v1-2-e9059776f85c@qti.qualcomm.com/ Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add the base USB devicetree definitions for Kaanapali platform. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260329175249.2946508-2-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Enable USB support on Kaanapali MTP variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260329175249.2946508-3-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Enable USB support on Kaanapali QRD variant. Enable USB controller in device mode till glink node is added. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260329175249.2946508-4-krishna.kurapati@oss.qualcomm.com/ Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Add the Adreno GPU SMMU node for kaanapali platform. Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Add GPU and GMU devicetree nodes for the Adreno 840 GPU found on Qualcomm Kaanapali platform. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Add the secure firmware name property and enable GPU support on Kaanapali QRD device. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Add the secure firmware name property and enable GPU support on Kaanapali MTP device. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Dipa Mantre <dipa.mantre@oss.qualcomm.com> Reviewed-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260415-cpufreq_kaanapali-v1-1-1fa94105d5c2@oss.qualcomm.com
Add support for SYSTEM_RESET2 vendor-specific resets in qcs615-ride as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/all/20251015-arm-psci-system_reset2-vendor-reboots-v16-14-b98aedaa23ee@oss.qualcomm.com/ Signed-off-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
Enable cdsp cooling devices and thermal zone cooling map bindings for cdsp. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251223123227.1317244-7-gaurav.kohli@oss.qualcomm.com
Add PSCI SYSTEM_RESET2 reboot-modes for talos based boards, for use by the psci_reboot_mode driver. The following modes are defined: - bootloader: reboot into fastboot mode for fastboot flashing. - edl: reboot into emergency download mode for image loading via the Firehose protocol. Support for these modes is firmware dependent. Link: https://lore.kernel.org/all/20260304-arm-psci-system_reset2-vendor-reboots-v20-10-cf7d346b8372@oss.qualcomm.com/ Signed-off-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
…MI2S1 TLMM pins This patch adds the Generic Pack Router (GPR) node together with Audio Process Manager (APM) and Proxy Resource Manager (PRM) audio service nodes to the Talos device tree description. It also introduces MI2S1 pinctrl states for data0, data1, sck, and ws lines, grouped into a single entry at the SoC-level DTSI for better reuse and clarity. Link: https://lore.kernel.org/all/20260409030156.155455-2-le.qi@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
…7212 codec Add the sound card node for QCS615 Talos EVK with DA7212 codec connected over the Primary MI2S interface. The configuration enables headphone playback and headset microphone capture, both of which have been tested to work. Link: https://lore.kernel.org/all/20260409030156.155455-3-le.qi@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
Enable GPU for talos-evk-som platform and provide path for zap shader. Link: https://lore.kernel.org/all/20260427-talos-evt-gpu-v1-1-d40b6dffa108@oss.qualcomm.com/ Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
# Conflicts: # arch/arm64/boot/dts/qcom/kaanapali.dtsi
# Conflicts: # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Name SHA Commits
tech/bsp/clk 95651c6 7
tech/bsp/soc-infra 20c09ce 3
tech/bsp/pinctrl 3f1acf8 1
tech/bsp/remoteproc df5635b 5
tech/bus/peripherals 287f0f5 8
tech/bus/pci/all 13f302c 9
tech/bus/pci/phy aaf8ef1 4
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 8c7f91d 35
tech/debug/hwtracing 25c6a74 30
tech/pmic/misc eee20da 1
tech/pmic/regulator 81fc8fb 6
tech/mem/iommu 1fa98cb 5
tech/mm/audio/all cab3357 10
tech/mm/camss bc49180 26
tech/mm/drm 2daf24f 21
tech/mm/fastrpc c29b2a8 5
tech/mm/phy 56ccbf4 1
tech/mm/video 72e188f 29
tech/net/ath 74680bd 4
tech/net/phy a3602e9 1
tech/net/bluetooth 10b91ca 1
tech/pm/power c7d3312 8
tech/pm/thermal 90f2db5 5
tech/security/crypto a6ce790 12
tech/security/ice 1564b82 25
tech/storage/phy cf1667f 1
tech/storage/all e254dae 1
tech/all/dt/qcs6490 698ef09 17
tech/all/dt/qcs9100 e276717 18
tech/all/dt/qcs8300 90ba006 15
tech/all/dt/qcs615 9292d38 8
tech/all/dt/agatti c828f10 1
tech/all/dt/hamoa 33384fe 28
tech/all/dt/glymur 9741caf 19
tech/all/dt/kaanapali 7436a08 9
tech/all/dt/pakala 705ac54 6
tech/all/config 771ebbc 58
tech/overlay/dt abfeee7 39
tech/all/workaround 3809f96 13
tech/mproc/all 0aa90b7 3
tech/noup/debug/all 53e8e4b 24
tech/hwe/unoq b2ea57b 5