Add registers to the DCC linked lists for multiple QCOM platforms#546
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jiegan0107 wants to merge 6 commits intoqualcomm-linux:qcom-6.18.yfrom
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Add registers to the DCC linked lists for multiple QCOM platforms#546jiegan0107 wants to merge 6 commits intoqualcomm-linux:qcom-6.18.yfrom
jiegan0107 wants to merge 6 commits intoqualcomm-linux:qcom-6.18.yfrom
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Add the full DCC register capture list for the Lemans platform derived from debug_config_qcs9100.sh. The registers cover LPM, TSENS, PLL, LIMITS, and DDR subsystems, all configured on linked list 6 to match the runtime script (LLNUM=6 in configure_dcc()). Consecutive single-word reads are merged into burst entries (e.g. "R addr N") to keep the array compact; the kernel driver merges them identically via dcc_config_add(). Estimated SRAM usage is ~19 KB, within the 24 KB (0x6000) budget for the Lemans DCC RAM. Move the lemans DCC configuration (entries array, link config, dcc config, and pdata) into a dedicated header qcom-dcc-lemans-config.h to avoid bloating qcom-dcc-dev.c with the large register table. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Move the talos DCC configuration (entries array, link config, dcc config, and pdata) into a dedicated header qcom-dcc-talos-config.h, consistent with the approach used for the lemans config. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
The lemans_pdata is shared by both Lemans (534, 667, 676) and Monaco (606, 674, 675) SoC variants. Add comments to distinguish the two groups and reorder the case labels accordingly. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the full DCC register capture list for the Kodiak platform derived
from debug_config_qcm6490.sh. The registers are distributed across
three linked lists:
- Link list 6: pcu, epss, pimem, core, gemnoc, tsens, spmi, gpu,
sysnoc, aggrenoc, gcc (430 entries)
- Link list 4: confignoc, limits, gic, mmssnoc, apps_rsc, misc, ddr
(450 entries)
- Link list 3: lpass_rsc, nsp_rsc, sdi_debug, lpass_cdsp_tunning,
wpss_rsc, video_noc (231 entries)
Estimated SRAM usage is ~14 KB, well within the 24 KB (0x6000) budget.
Move the kodiak DCC configuration (entries arrays, link configs, dcc
config, and pdata) into a dedicated header qcom-dcc-kodiak-config.h,
consistent with the approach used for talos and lemans.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the DCC register capture list for the Pakala platform. The registers are distributed across two linked lists: - Link list 6: 910 entries - Link list 4: 212 entries Estimated SRAM usage is ~15 KB, within the 16 KB (0x4000) budget. Move the pakala DCC configuration (entries arrays, link configs, dcc config, and pdata) into a dedicated header qcom-dcc-pakala-config.h, consistent with the approach used for other platforms. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…' into qcom-6.18.y
shashim-quic
approved these changes
May 7, 2026
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Add registers to the DCC linked list for below QCOM platforms:
Kodiak
Lemans
Monaco
Pakala
CRs-Fixed: 4527479