feat(runtime): deferred INTC pending-raise latch with per-tick drain

ps2xRecomp/include/ps2recomp/elf_parser.h

@@ -1,6 +1,7 @@
 #ifndef PS2RECOMP_ELF_PARSER_H
 #define PS2RECOMP_ELF_PARSER_H
 
+#include <cstdint>
 #include <elfio/elfio.hpp>
 #include <string>
 #include <vector>

ps2xRuntime/include/runtime/ps2_memory.h

@@ -343,6 +343,7 @@ class PS2Memory
     void processVIF1Data(const uint8_t *data, uint32_t sizeBytes);
     void processPendingTransfers();
     std::vector<uint32_t> consumeCompletedDmacCauses();
+    uint32_t consumeVif1InterruptEdges();
 
     int pollDmaRegisters();
 
@@ -420,6 +421,7 @@ class PS2Memory
     std::vector<PendingTransfer> m_pendingVif1Transfers;
     std::mutex m_completedDmacMutex;
     std::vector<uint32_t> m_completedDmacCauses;
+    std::atomic<uint32_t> m_vif1InterruptEdges{0u}; // I-bit VIFcodes seen since last consume
 
     struct CodeRegion
     {

ps2xRuntime/src/lib/Kernel/Stubs/Helpers/Support.h

@@ -1,6 +1,11 @@
 #include <algorithm>
 #include <cctype>
 
+namespace ps2_syscalls
+{
+    void raisePendingIntc(uint32_t cause);
+}
+
 namespace
 {
     constexpr uint32_t kCdSectorSize = 2048;
@@ -1436,6 +1441,15 @@ namespace
             ps2_syscalls::dispatchDmacHandlersForCause(rdram, runtime, completedCause);
         }
 
+        // VIF1 INTC cause 5 is asserted by a VIFcode I bit, decoded during the
+        // processPendingTransfers() parse above. Raise only when such an edge was
+        // actually seen. Delivery stays deferred to the next drain: sce libdma
+        // registers the cause-5 handler after this kick returns.
+        if (mem.consumeVif1InterruptEdges() != 0u)
+        {
+            ps2_syscalls::raisePendingIntc(5u);
+        }
+
         return 0;
     }
 

ps2xRuntime/src/lib/Kernel/Syscalls/Interrupt.cpp

@@ -3,6 +3,8 @@
 #include "ps2_log.h"
 #include "Stubs/GS.h"
 
+#include <bit>
+
 namespace ps2_syscalls
 {
     namespace interrupt_state
@@ -24,10 +26,35 @@ namespace ps2_syscalls
         uint32_t g_enabled_dmac_mask = 0xFFFFFFFFu;
         uint64_t g_vsync_tick_counter = 0u;
         VSyncFlagRegistration g_vsync_registration{};
+
+        std::atomic<uint32_t> g_pending_intc_causes{0u};              // bitmask, one pending bit per cause
+        std::atomic<int64_t> g_pending_intc_raise_ns[32] = {}; // steady_clock ns at last raise, per cause
+        // The raise-timestamp entries are atomic because raisePendingIntc (any
+        // thread) stores a fresh timestamp while the interrupt worker thread
+        // reads it in drainPendingIntc.
     }
 
     using namespace interrupt_state;
 
+    namespace
+    {
+        SteadyNowFn g_pendingIntcNowFn{}; // empty = real clock
+
+        int64_t now_ns()
+        {
+            const auto tp = g_pendingIntcNowFn ? g_pendingIntcNowFn()
+                                                : std::chrono::steady_clock::now();
+            return std::chrono::duration_cast<std::chrono::nanoseconds>(
+                       tp.time_since_epoch())
+                .count();
+        }
+    }
+
+    void setPendingIntcClockForTest(SteadyNowFn fn)
+    {
+        g_pendingIntcNowFn = std::move(fn);
+    }
+
     static void writeGuestU32NoThrow(uint8_t *rdram, uint32_t addr, uint32_t value)
     {
         if (addr == 0u)
@@ -96,19 +123,19 @@ namespace ps2_syscalls
         return (s_cachedStackTop != 0u) ? s_cachedStackTop : (PS2_RAM_SIZE - 0x10u);
     }
 
-    static void dispatchIntcHandlersForCause(uint8_t *rdram, PS2Runtime *runtime, uint32_t cause)
+    static int dispatchAndCountIntcHandlersForCause(uint8_t *rdram, PS2Runtime *runtime, uint32_t cause)
     {
         if (!rdram || !runtime)
         {
-            return;
+            return 0;
         }
 
         std::vector<IrqHandlerInfo> handlers;
         {
             std::lock_guard<std::mutex> lock(g_irq_handler_mutex);
             if (cause < 32u && (g_enabled_intc_mask & (1u << cause)) == 0u)
             {
-                return;
+                return 0;
             }
 
             handlers.reserve(g_intcHandlers.size());
@@ -133,6 +160,7 @@ namespace ps2_syscalls
                       { return a.order < b.order; });
         }
 
+        int dispatchedCount = 0;
         for (const IrqHandlerInfo &info : handlers)
         {
             if (!runtime->hasFunction(info.handler))
@@ -157,6 +185,7 @@ namespace ps2_syscalls
                 continue;
             }
 
+            ++dispatchedCount;
             try
             {
                 R5900Context irqCtx{};
@@ -216,6 +245,96 @@ namespace ps2_syscalls
                 }
             }
         }
+
+        return dispatchedCount;
+    }
+
+    void raisePendingIntc(uint32_t cause)
+    {
+        if (cause >= 32u || cause == kIntcVblankStart || cause == kIntcVblankEnd)
+        {
+            return;
+        }
+
+        const uint32_t bit = 1u << cause;
+        g_pending_intc_raise_ns[cause].store(now_ns(), std::memory_order_relaxed); // every raise
+        const uint32_t prev = g_pending_intc_causes.fetch_or(bit, std::memory_order_acq_rel);
+        if ((prev & bit) == 0u)
+        {
+            PS2_IF_AGRESSIVE_LOGS({
+                static std::atomic<uint32_t> s_raiseLogCount{0u};
+                const uint32_t logIndex = s_raiseLogCount.fetch_add(1u, std::memory_order_relaxed);
+                if (logIndex < 16u || (logIndex % 256u) == 0u)
+                {
+                    RUNTIME_LOG("[INTC:raise] cause=" << cause);
+                }
+            });
+        }
+    }
+
+    void drainPendingIntc(uint8_t *rdram, PS2Runtime *runtime)
+    {
+        uint32_t pending = g_pending_intc_causes.load(std::memory_order_acquire);
+        while (pending != 0u)
+        {
+            const uint32_t cause = static_cast<uint32_t>(std::countr_zero(pending));
+            const uint32_t bit = 1u << cause;
+            pending &= ~bit;
+
+            const int ran = dispatchAndCountIntcHandlersForCause(rdram, runtime, cause);
+            if (ran > 0)
+            {
+                // Level-triggered: concurrent same-cause raises collapse into one delivery (intentional).
+                g_pending_intc_causes.fetch_and(~bit, std::memory_order_acq_rel);
+                PS2_IF_AGRESSIVE_LOGS({
+                    static std::atomic<uint32_t> s_deliverLogCount{0u};
+                    const uint32_t logIndex = s_deliverLogCount.fetch_add(1u, std::memory_order_relaxed);
+                    if (logIndex < 16u || (logIndex % 256u) == 0u)
+                    {
+                        RUNTIME_LOG("[INTC:deliver] cause=" << cause << " handlers=" << ran);
+                    }
+                });
+            }
+            else
+            {
+                const int64_t age = now_ns() - g_pending_intc_raise_ns[cause].load(std::memory_order_relaxed);
+                if (age > kPendingIntcMaxAgeNs)
+                {
+                    g_pending_intc_causes.fetch_and(~bit, std::memory_order_acq_rel);
+                    PS2_IF_AGRESSIVE_LOGS({
+                        static std::atomic<uint32_t> s_dropLogCount{0u};
+                        const uint32_t logIndex = s_dropLogCount.fetch_add(1u, std::memory_order_relaxed);
+                        if (logIndex < 16u || (logIndex % 256u) == 0u)
+                        {
+                            RUNTIME_LOG("[INTC:drop] cause=" << cause << " aged out with no registered/enabled handler");
+                        }
+                    });
+                }
+            }
+        }
+    }
+
+    void resetInterruptHandlerState()
+    {
+        {
+            std::lock_guard<std::mutex> lock(g_irq_handler_mutex);
+            g_intcHandlers.clear();
+            g_dmacHandlers.clear();
+            g_nextIntcHandlerId = 1;
+            g_nextDmacHandlerId = 1;
+            g_intc_head_order = 0;
+            g_intc_tail_order = 1000;
+            g_dmac_head_order = 0;
+            g_dmac_tail_order = 1000;
+            g_enabled_intc_mask = 0xFFFFFFFFu;
+            g_enabled_dmac_mask = 0xFFFFFFFFu;
+        }
+        g_pending_intc_causes.store(0u, std::memory_order_release);
+        for (auto &ts : g_pending_intc_raise_ns)
+        {
+            ts.store(0, std::memory_order_relaxed);
+        }
+        setPendingIntcClockForTest(nullptr); // a leaked fake clock would leak into the next test
     }
 
     void dispatchDmacHandlersForCause(uint8_t *rdram, PS2Runtime *runtime, uint32_t cause)
@@ -408,15 +527,16 @@ namespace ps2_syscalls
                     PS2Runtime::DeferredGuestYieldScope deferYield(reschedulePending);
                     const uint64_t tickValue = signalVSyncFlag(rdram, runtime);
                     ps2_stubs::dispatchGsSyncVCallback(rdram, runtime, tickValue);
-                    dispatchIntcHandlersForCause(rdram, runtime, kIntcVblankStart);
+                    dispatchAndCountIntcHandlersForCause(rdram, runtime, kIntcVblankStart);
                     handoffBaseline = runtime->guestExecutionHandoffEpochSnapshot();
                 }
                 if (reschedulePending && !runtime->isStopRequested())
                 {
                     runtime->waitForGuestExecutionHandoff(handoffBaseline);
                 }
                 std::this_thread::sleep_for(std::chrono::microseconds(500));
-                dispatchIntcHandlersForCause(rdram, runtime, kIntcVblankEnd);
+                dispatchAndCountIntcHandlersForCause(rdram, runtime, kIntcVblankEnd);
+                drainPendingIntc(rdram, runtime);
             }
         }
 

ps2xRuntime/src/lib/Kernel/Syscalls/Interrupt.h

@@ -1,6 +1,10 @@
 #pragma once
 
+#include <atomic>
+#include <chrono>
 #include <condition_variable>
+#include <cstdint>
+#include <functional>
 #include "ps2_syscalls.h"
 
 namespace ps2_syscalls
@@ -24,9 +28,18 @@ namespace ps2_syscalls
         extern uint32_t g_enabled_dmac_mask;
         extern uint64_t g_vsync_tick_counter;
         extern VSyncFlagRegistration g_vsync_registration;
+        extern std::atomic<uint32_t> g_pending_intc_causes;
+        constexpr int64_t kPendingIntcMaxAgeNs = 2'000'000'000; // ~2 s wall-clock
     }
 
     void dispatchDmacHandlersForCause(uint8_t *rdram, PS2Runtime *runtime, uint32_t cause);
+    void raisePendingIntc(uint32_t cause);
+    void drainPendingIntc(uint8_t *rdram, PS2Runtime *runtime);
+    // Test-support: reset all INTC/DMAC handler bookkeeping to process-start
+    // defaults so regression tests are order-independent.
+    void resetInterruptHandlerState();
+    using SteadyNowFn = std::function<std::chrono::steady_clock::time_point()>;
+    void setPendingIntcClockForTest(SteadyNowFn fn); // nullptr restores steady_clock::now
     void EnsureVSyncWorkerRunning(uint8_t *rdram, PS2Runtime *runtime);
     uint64_t GetCurrentVSyncTick();
     void stopInterruptWorker();

ps2xRuntime/src/lib/ps2_memory.cpp

@@ -297,6 +297,7 @@ bool PS2Memory::initialize(size_t ramSize)
         std::lock_guard<std::mutex> lock(m_completedDmacMutex);
         m_completedDmacCauses.clear();
     }
+    m_vif1InterruptEdges.store(0u, std::memory_order_relaxed);
     m_codeRegions.clear();
     m_path3Masked = false;
     m_path3MaskedFifo.clear();
@@ -1665,6 +1666,11 @@ std::vector<uint32_t> PS2Memory::consumeCompletedDmacCauses()
     return causes;
 }
 
+uint32_t PS2Memory::consumeVif1InterruptEdges()
+{
+    return m_vif1InterruptEdges.exchange(0u, std::memory_order_relaxed);
+}
+
 void PS2Memory::flushMaskedPath3Packets(bool drainImmediately)
 {
     if (m_path3Masked || m_path3MaskedFifo.empty())

ps2xRuntime/src/lib/ps2_runtime.cpp

@@ -9,6 +9,7 @@
 #include "Kernel/Stubs/Audio.h"
 #include "Kernel/Stubs/GS.h"
 #include "Kernel/Stubs/MPEG.h"
+#include "Kernel/Syscalls/Interrupt.h"
 #include "ps2_host_backend.h"
 #include "ps2_iop_host.h"
 #include "ps2x/iop/iop_subsystem.h"
@@ -1404,6 +1405,15 @@ void PS2Runtime::drainCompletedDmacHandlers(uint8_t *rdram)
     {
         ps2_syscalls::dispatchDmacHandlersForCause(rdram, this, cause);
     }
+
+    // Catch-all for VIF1 I-bit edges parsed outside submitDmaSend's own
+    // consume (GS/Font/GIF-chain paths that call processVIF1Data within the
+    // frame) so they get delivered here instead of leaking into a later,
+    // unrelated submitDmaSend kick.
+    if (m_memory.consumeVif1InterruptEdges() != 0u)
+    {
+        ps2_syscalls::raisePendingIntc(5u);
+    }
 }
 
 void PS2Runtime::handleTrap(uint8_t *rdram, R5900Context *ctx)

ps2xRuntime/src/lib/ps2_vif1_interpreter.cpp

@@ -309,7 +309,11 @@ void PS2Memory::processVIF1Data(const uint8_t *data, uint32_t sizeBytes)
         vif1_regs.code = cmd;
         vif1_regs.num = num;
         if (irq)
+        {
             vif1_regs.stat |= (1u << 11); // INT
+            // Record the VIF1 INT edge for the deferred cause-5 raise.
+            m_vif1InterruptEdges.fetch_add(1u, std::memory_order_relaxed);
+        }
 
         if (opcode == VIF_NOP)
         {