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Adds support for AArch64 SVE to inline assembly - #158312

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Adds support for AArch64 SVE to inline assembly#158312
CrooseGit wants to merge 3 commits into
rust-lang:mainfrom
CrooseGit:dev/reucru01/sve-asm-support

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rustbot commented Jun 23, 2026

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rustc_codegen_cranelift is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_cranelift instead.

cc @bjorn3

rustc_codegen_gcc is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_gcc instead.

cc @antoyo, @GuillaumeGomez

@rustbot rustbot added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Jun 23, 2026
@rustbot rustbot added the T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. label Jun 23, 2026
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rustbot commented Jun 23, 2026

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r? @nikomatsakis

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@CrooseGit
CrooseGit force-pushed the dev/reucru01/sve-asm-support branch from 544d13e to 29690b5 Compare June 24, 2026 10:11
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r? compiler

@rustbot rustbot assigned tiif and unassigned nikomatsakis Jul 6, 2026
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tiif commented Jul 9, 2026

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r? compiler

@rustbot rustbot assigned hanna-kruppe and unassigned tiif Jul 9, 2026
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@rustbot rustbot assigned TaKO8Ki and unassigned hanna-kruppe Jul 11, 2026
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r? @Amanieu

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Also blesses existing tests to make way for sve asm support
@davidtwco
davidtwco force-pushed the dev/reucru01/sve-asm-support branch from 29690b5 to 140fb02 Compare August 19, 2026 10:47
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rustbot commented Aug 19, 2026

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This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

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Facilitates scalable vector support in inline assembly.
Adds new `zreg` register type and `SveVec*` variants to `InlineAsmType`
@davidtwco
davidtwco force-pushed the dev/reucru01/sve-asm-support branch from 140fb02 to 5a331e4 Compare August 19, 2026 11:04
@Amanieu

Amanieu commented Aug 23, 2026

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Finally getting around to reviewing this, sorry for the delay.

Why did you choose to make zreg a separate register class from vreg? I feel that the design would be much cleaner if all we did was enable more types to be used with vreg when the sve feature is available.

Other than that detail, the rest of the code mostly looks correct.

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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.

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9 participants