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Feature: Clearing Charge/Discharge Slots When Disabled#3889

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CraigCallender wants to merge 2 commits intospringfall2008:mainfrom
CraigCallender:feature/clear-times-on-slot-disable
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Feature: Clearing Charge/Discharge Slots When Disabled#3889
CraigCallender wants to merge 2 commits intospringfall2008:mainfrom
CraigCallender:feature/clear-times-on-slot-disable

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Fix: Clear Stale Slot Times When Disabling Charge/Discharge Windows (Solax Modbus FB00)

Similar to #3787 but for inverters using the Solax Modbus Integration (I've recently switched over to this).

Problem

When Predbat controls a Solax Modbus inverter (GS_fb00 firmware) via Home Assistant entities, disabling a timed charge or discharge window can leave stale time and current values in the inverter's registers. On the next enable cycle, when Predbat writes a new time window, the inverter's overlap validation can reject the write because it sees the stale times from the previous disable as conflicting with the new active slot, even though the slot was supposedly disabled.

This manifests as silent write failures where the inverter silently rejects the command, leaving Predbat unaware that the new window was not applied.

Changes

config.py — New clear_slot_on_disable capability flag

Added a new per-inverter-type capability flag "clear_slot_on_disable" (defaults to False for all types):

  • GS_fb00 (Ginlong Solis FB00 firmware): True
  • All other inverter types: False (unchanged behavior)

This flag is loaded in Inverter.__init__ as self.inv_clear_slot_on_disable.

inverter.py — Clear slot values on disable

New clear_timed_slot_values(direction) method

Clears all timed slot values (times and current) for a charge or discharge direction. The method:

  1. Returns early (with a log message) if inv_clear_slot_on_disable is False (no-op for inverters that don't need this).
  2. Detects the configured time format ("H M", "H:M-H:M", or other) and logs it.
  3. Writes 00:00:00 (or 0) to all time and minute entities, and 0 to the timed current entity.
  4. Tracks write failures and reports them as warnings via record_status() if any writes fail.
  5. Logs validation errors if an invalid direction is passed.

Integration into disable paths

The method is called unconditionally after disabling:

  • adjust_force_export(force_export=False, ...) — calls clear_timed_slot_values("discharge") after turning off the discharge enable switch.
  • disable_charge_window() — calls clear_timed_slot_values("charge") after turning off the charge enable switch (when inv_has_charge_enable_time is True).

The guard for inv_clear_slot_on_disable is inside the method, so call sites are simple and don't need to check the flag.

docs/inverter-setup.md — Documentation update

Added clear_slot_on_disable to the custom inverter settings reference section, documenting:

  • Purpose: prevents inverters that validate for overlapping time slots from rejecting writes when switching between charge and discharge modes.
  • Current scope: tested only with GS_fb00 (Ginlong Solis FB00 firmware) inverters via Solax Modbus.
  • Default: False for all other inverter types.

tests/test_inverter.py — New tests

  • test_disable_charge_window_clears_slot_values_hm — verifies that disabling a charge window clears H M format time entities (hour/minute numbers and time.* entities) back to 0 or 00:00:00, and resets timed charge current to 0.
  • test_disable_discharge_clears_slot_values_time_entities — verifies that disabling a discharge window clears time.* entities to 00:00:00 and resets timed discharge current to 0.

Both tests set inv_clear_slot_on_disable = True to enable the clearing behavior and validate that the slot values are actually written.

Testing

All existing inverter tests pass. New tests added to validate:

  • Charge window disable clears H M format slots
  • Discharge window disable clears time.* format slots
  • Stale writes are tracked and reported as warnings
  • The feature is a no-op when the capability flag is False

…ilure on solis fb00 firmware if times overlap (even with disabled slots).
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Pull request overview

Adds a per-inverter capability to proactively clear timed charge/discharge slot registers (times + current) when disabling schedules, addressing Solax Modbus FB00 overlap-validation failures caused by stale slot values.

Changes:

  • Introduces clear_slot_on_disable inverter capability (enabled for GS_fb00) and wires it into Inverter initialization.
  • Adds Inverter.clear_timed_slot_values(direction) and invokes it after disabling charge/discharge schedules.
  • Updates documentation and extends inverter tests to verify slot values are cleared on disable.

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 1 comment.

File Description
docs/inverter-setup.md Documents the new clear_slot_on_disable capability and its intended scope/default.
apps/predbat/config.py Enables clear_slot_on_disable for GS_fb00 inverter type definition.
apps/predbat/inverter.py Adds slot-clearing logic and calls it from charge/discharge disable paths.
apps/predbat/tests/test_inverter.py Adds coverage to ensure disable paths clear times/minutes/current back to zero.

Comment thread apps/predbat/inverter.py
even when a slot is disabled. Does nothing if inv_clear_slot_on_disable is False.
"""
if not self.inv_clear_slot_on_disable:
self.log(f"Inverter {self.id} clear_timed_slot_values: skipped (clear_slot_on_disable not set for this inverter type)")
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2 participants