Updated the Affiliation of Authors

[chennakeshavadasa]

This work presents an $R_{on}/g_m$ based design methodology for Inverter based dynamic amplifiers (IBA), addressing a fundamental gap in existing approaches where the large-signal RC settling phase governed by the final stage device ON resistance $R_{on}$ remains uncharacterized until post-simulation. Unlike the conventional $g_m/I_D$ methodology, which targets only the small-signal transconductance, the proposed approach simultaneously co-designs both settling phases through pre-characterized device look-up tables (LUTs) derived from parametric SPICE simulations in the IHP SG13G2 130 nm BiCMOS process. These LUTs take into consideration of $R_{on}/g_m$ as a function of device geometry, bias, and process corner, making worst-case corner behavior and valid bias deadzone boundaries directly readable at the design entry stage without iterative simulation. A head-to-head comparison with the $g_m/I_D$ methodology confirms that the $R_{on}/g_m$ approach achieves equivalent settling accuracy while substantially reducing design cycles and providing more useful information regarding deadzone bias requirement by surfacing process-corner sensitivity upfront.

Team

Name	Affiliation	IEEE	SSCS	Contact
Nithin P	IIT Gandhinagar	Yes	Yes	nithinpurushothama@gmail.com
Pramoda S R	B.Tech, VTU	—	—	pramoda9.2.2004@gmail.com
S Suyajnaa Jagannath Gowda	B.Tech, VTU	—	—	suyajnaa@gmail.com
Runpeng Gao	PhD, Oregon State University	Yes	Yes	rppgao@gmail.com
Praveen Kumar Venkatachala	PhD, Oregon State University	Yes	Yes	vpravin.8@gmail.com
Prof. Madhav K Pathak	Asst. Professor, EE Dept, IIT Gandhinagar	Yes	Yes	madhav.pathak@iitgn.ac.in