coreboot: lemp12: Enable TCSS Type-C port, PMC mux and retimer

[mattwollf]

Fixes #675 — lemp12's USB-C port (J_TYPEC1) never exceeds USB 2.0 and DisplayPort
alt-mode never engages.

Cause. fill_fsps_tcss_params() in soc/intel/alderlake/fsp_params.c derives the
FSP-S UPD UsbTcPortEn from whether the devicetree device tcss_usb3_port1 is enabled.
soc/intel/alderlake/chipset.cb defaults it off, the rpl baseboard declares no TCSS
section, and no rpl variant enables it — so the bit stays clear and FSP-S never brings
the Type-C port up. The connector's USB2 pair routes to the PCH (usb2_ports[2] = USB2_PORT_TYPE_C) and keeps working, which is why devices enumerate at 480 Mbps while
the SuperSpeed lanes stay dark.

All 7/7 adl variants enable tcss_usb3_port1; 0/12 rpl variants do. tgl-u and
mtl also enable it, so this looks like the rpl directory having been created without
carrying the Type-C stack over rather than a per-board decision.

This PR is a coreboot submodule bump. The change is entirely inside coreboot, so
there is nothing else for firmware-open to carry. The gitlink points at
mattwollf/coreboot@3f55b23,
branch lemp12-tcss-s76,
based on 28fb5085 — the exact commit this repo currently pins. It will not resolve
until the two commits are on system76/coreboot; tell me where you want them (a PR
there, or coreboot Gerrit) and I'll move them. The full diff is inline below so it is
reviewable without chasing the fork.

Two commits, 2 files, +80/-1:

• mb/system76/rpl: select DRIVERS_INTEL_PMC and DRIVERS_INTEL_USB4_RETIMER. adl
  selects both, rpl neither, and the chip entries below don't link without them. No
  functional effect on variants that don't use the drivers.
• mb/system76/lemp12: enable tcss_root_hub / tcss_usb3_port1 under tcss_xhci, add
  drivers/intel/usb4/retimer under tcss_dma0, add drivers/intel/pmc_mux + conn
  under pmc, and add the per-port drivers/usb/acpi descriptors under xhci. Mirrors
  lemp11.

GPP_E4 for the retimer force-power pad is the board's own TBT_FORCE_PWR, cross-checked
against the Clevo L140AU schematic (6-71-L14A0-D02A): PCH ball FC22 →
GPPE4_TBT_FORCE_PWR → R411 (0 Ω, populated) → TC_RETIMER_FORCE_PWR → JHL8040R
FORCE_PWR ball A9.

On the drivers/usb/acpi hunk. CB:94134 adds those per-port descriptors to all twelve
rpl variants and is a better version of that part, but it isn't on the system76 branch
yet and the pmc_mux conn node references usb2_port3 — so it's included here. Drop that
hunk if 94134 is picked up first.

What is verified

• Builds and links for lemp12 on the pinned coreboot (28fb5085, release
  2025-07-24_c242738).
• Generated static.c: _dev_tcss_usb3_port1.enabled is 0 before and 1 after; the tree
  gains drivers_intel_pmc_mux_ops, drivers_intel_pmc_mux_conn_ops and
  drivers_intel_usb4_retimer_ops; conn.usb2_port resolves to &_dev_usb2_port3 and
  conn.usb3_port / retimer.dfp[0].typec_port to &_dev_tcss_usb3_port1.
• Stock vs patched ROM built from the same tree: identical CBFS file set; FSP, microcode,
  payload and bootblock bit-for-bit unchanged; fallback/ramstage +2189 B, romstage
  +768 B. INTC105C appears only in the patched ramstage, and decoding the device array
  out of the extracted ramstage shows tcss_usb3_port1.enabled going 0 → 1 — so the bit
  reaches the image that would be flashed.

What is not verified — I have not flashed this. lemp12's SPI is a leadless WSON-8
MX25L25673G (U41), I have no external programmer, and the flash map has a single
COREBOOT region with no recovery slot, so a bad image is unrecoverable on my only
machine. The runtime behaviour is genuinely untested. If someone there can flash it on a
bench unit it's a couple of minutes' work, and I'd rather that happen before anything here
claims to be tested.

Scope. lemp12 only, deliberately. Reading the other overridetrees, darp9, galp7 and
oryp11 look affected identically — in each case the Type-C connector with no PCH
usb3_ports[] entry is the one users report broken (#472 for oryp11, #497 for darp9,
where the reporter notes the adjacent Type-C works and a warranty mainboard swap changed
nothing). I don't own those boards, so I've left them alone; the same blocks should apply
with the conn alias and retimer pad adjusted per board. Happy to send them as a
follow-up.

No models/lemp12/coreboot.config change is needed; the two new Kconfig symbols are
selected by the rpl mainboard.

Full coreboot diff (2 files, +80/-1)

diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig
index b4b71d5bdb..3779c39229 100644
--- a/src/mainboard/system76/rpl/Kconfig
+++ b/src/mainboard/system76/rpl/Kconfig
@@ -8,6 +8,8 @@ config BOARD_SYSTEM76_RPL_COMMON
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_LOCKDOWN
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
index c84628b6ac..bff6e8d2a4 100644
--- a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
+++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb
@@ -12,8 +12,23 @@ chip soc/intel/alderlake
 		device ref tbt_pcie_rp0 on end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
 		end
-		device ref tcss_dma0 on end
 		device ref xhci on
 			register "usb2_ports" = "{
 				[0] = USB2_PORT_MID(OC_SKIP),		/* Type-A Left */
@@ -28,6 +43,56 @@ chip soc/intel/alderlake
 				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-A Right */
 				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* 3G/LTE */
 			}"
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 3G/LTE""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port3 on end
+					end
+				end
+			end
 		end
 
 		device ref i2c0 on
@@ -84,5 +149,17 @@ chip soc/intel/alderlake
 				.pcie_rp_detect_timeout_ms = 50,
 			}"
 		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC1
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
 	end
 end

[crawfxrd]

Patches for submodules need to go to our forks, not changing the forks itself.