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Phase 4: tiny-gpu backend (memory plan, Kernel IR, registers, .tgpu) - #4
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Lower the legalized Graph IR to tiny-gpu SIMT kernels: one thread per output element (block = row, thread = column, tid = flat index), one kernel per op with fused epilogues staying a single launch. Add a liveness-based memory planner, the Kernel IR with printer, verifier and flatten-to-instructions, a linear-scan register allocator that never writes R5-R7 (asserted, and checked on the simulator), `.tgpu` assembly with source positions, a launch document with JSON Schema and spec, a static cost model, and an independent Kernel IR interpreter whose counts must equal the simulator's exactly. `tinyc --target gpu` gains --emit kernel|tgpu|launch, --run (real simulator, seeded inputs, measured vs estimated), --stats and --gpu-regs. The runner runs multi-launch programs with memory carried over and a fresh simulator per kernel. All examples, including the chained-matmul mlp_gpu, run bit-exact, and the same program gives identical results on tiny-gpu and tiny-tpu. Measured tiny-gpu facts are pinned in the target contract test: a label starting with R is parsed as a register, a loop of K iterations costs K cycles, relu costs a cycle only when a thread does not clamp, and branching to the end of a program costs a stray cycle. Tests: kernel IR and verifier, memory plan (incl. random programs), register allocator (loop-aware liveness, pressure errors), schema validation, every example on the real simulator, estimate bounds attained at data extremes, pinned cost numbers, and Hypothesis properties over generated programs.
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Stacked on feat/phase-3-tpu-backend. Merge the stack in order, starting from the bottom PR.
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