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Phase 5: tiny-gpu kernel optimizations (-O1/-O2) - #5
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Add kernel passes on the Kernel IR: loop-invariant code motion, strength reduction of counter-driven address chains into bumped pointers, liveness based dead-code elimination, shared-memory tiling (cooperative copy into SHST, SYNCB, then SHLD), full unrolling of loops up to 16 iterations, and constant/copy folding. -O1 enables licm and strength reduction; -O2 adds tiling, unrolling and folding. Every pass is switchable by name. The Kernel IR gains SharedLoad, SharedStore and Barrier. The interpreter models tiny-gpu's barrier from its source (waiting threads re-execute SYNCB every step) and a test requires it to equal the simulator exactly on hand-written kernels whose threads arrive at different times. The cost model becomes an abstract interpretation: loads, stores, shared accesses and a tiled copy's guards are exact; only a branch on loaded data (relu) yields min/max bounds. Measured on the simulator (mm_relu 8x8): -O2 cuts instructions by 55% and global loads by 47% versus -O0, and cycles from 10 to 3. -O1/-O2 trade registers for instructions. The table is generated by scripts/opt_table.py into docs/ARCHITECTURE.md and a test fails if it drifts. Tests: directed tests per pass, the exact load formula (2MNK -> MK + MNK) on every matmul example, every level on the real simulator, kernels validated by the interpreter after each pass, and Hypothesis properties over generated programs. A pass-generated instruction without a source position was caught by the existing source-mapping test and fixed.
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Stacked on feat/phase-4-gpu-backend. Merge the stack in order, starting from the bottom PR.
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