One sweep, all segments: a line segment detector that reads the image exactly once — O(width) memory, integer-only streaming core — with HLS and Verilog RTL running live on an FPGA at 1080p30.
real-time computer-vision fpga hls image-processing verilog cpp17 low-latency edge-detection lsd embedded-vision vitis-hls streaming-algorithm line-segment-detection
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Updated
Aug 25, 2026 - C++