pipeline-verification

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Tharunreddym / riscv-pipeline-verification

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

c-plus-plus verification verilog scoreboard regression-testing systemverilog uvm constrained-random risc-v asic-verification questa dpi-c functional-coverage rtl-verification pipeline-verification

Updated May 19, 2026
SystemVerilog

DerathThutaram / riscv-hazard-verification

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RTL design and verification of hazard detection and forwarding logic for a 5-stage RISC-V pipeline.

riscv systemverilog hazard-detection design-verification pipeline-verification

Updated Oct 25, 2026
SystemVerilog

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