MLIR dialects for binary number representations.
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Updated
Jun 21, 2023 - C++
MLIR dialects for binary number representations.
RISC-V pipeline research: RV32IM soft core, branch prediction (SGF), FPGA experiments + paper
8 bit MCU design in Zedboard
Elastic Coarse-Grained Reconfigurable Architecture Generator
Organic set of software components that assists in implementing resilient distributed systems that excel in reconfigurability, monitorability, modularity, extensibility, and openness. It includes libraries of ready-to-use modules for Big Data data engineering, analytics, and visualization. It is designed with Reconfigurable Manufacturing in mind.
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
Verilog sources for FPGA Zybo board implementing vision algorithms.
Curated list of Deep Neural Networks on FPGAs research papers
Implementation of a (soft) coprocessor for the computation of a 16 bit LFSR.
Specification of the Base2 IR abstraction.
Microservice-based IOT architecture based on Raspberry Pi and Arduino to facilitate the plant science studies
Reconfigurable FPGA protocol bridge supporting UART, SPI, and I2C conversion using Verilog HDL on Nexys A7 with real-time ILA/VIO debugging.
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