Very simple Cortex-M1 SoC design based on ARM DesignStart
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Updated
Jan 25, 2022 - C
Very simple Cortex-M1 SoC design based on ARM DesignStart
C++ 17 Hardware abstraction layer generator from systemrdl
☕️ Adding Pressure Profiling to the Flair 58 Espresso Maker via linear actuators and an ESP32 microcontroller
AutumnOS: A locally developed, open-source Mobile Operating System for RISC-V. Powering embedded devices with Linux kernel.
A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.
A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.
A small APSoC project for testing Temperature and Relative Humidity readings of a IIC sensor
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This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC
SoC de Reproductor MP3 con filtros desarrollado en De1-SoC
Time: 2024 May to July; Utilized SystemVerilog to Implement Google dino game on an ili9341 display and two Seven-Segment Displays
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