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transistor-sizing

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chandansaipavanpadala / ultra-low-voltage-low-power-compressor

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Designed and simulated ultra low-voltage, low-power CMOS 5:2 compressors in Cadence Virtuoso, based on Figure 13 from the referenced IEEE paper. Focused on optimizing power, delay, and area for efficient high-speed arithmetic circuits used in VLSI and DSP applications.

dsp digital-logic vlsi cadence-virtuoso cadence transient-analysis cmos low-power microelectronics ic-design vlsi-design arithmetic-circuits 45nm layout-design power-delay-product drc-lvs transistor-sizing gpdk045 compressor-circuit ultra-low-voltage
  • Updated Mar 22, 2026

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