UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.
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Feb 26, 2025 - Verilog
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uvm-testbench
Here are 11 public repositories matching this topic...
SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).
dsp systemverilog soc uvm risc-v genus riscv32 asic-verification axi4 axi4-lite axi4-protocol asic-design xcelium neorv32 uvm-verification innovus cadence-xcelium axi4-lite-system-verilog uvm-testbench genus-synthesis
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Feb 5, 2026
UVM-based verification environment for an APB FIFO design with comprehensive test coverage and bug analysis.
systemverilog fifo uvm fifo-queue apb uvm-verification systemverilog-test-bench uvm-testbench apb-protocol
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Apr 3, 2026 - SystemVerilog
UVM-based verification environment for RISC-V Bit Manipulation Unit (BMU) covering key BitManip instructions
riscv systemverilog risc-v systemverilog-hdl bitmanipulation uvm-verification bitmanip uvm-testbench
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Sep 16, 2025 - SystemVerilog
Synchronous FIFO verified using UVM including functional coverage
verification rtl systemverilog uvm systemverilog-simulation asic-design uvm-verification uvm-testbench
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Apr 9, 2026 - SystemVerilog
UVM-based functional verification environment for a 1x3 packet router using SystemVerilog — includes driver, monitor, scoreboard, sequences, and coverage.
router assertions verilog scoreboard systemverilog vlsi questasim uvm verilog-hdl digital-design functional-verification asic-verification hardware-verification constrained-random-verification rtl-design packet-routing eda-tools uvm-testbench verification-environment vcs-simulator
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May 25, 2026 - SystemVerilog
Low-Power CGRA Design Methodology (WIP)
verilog vcs systemverilog synopsys hdl uvm hardware-acceleration parallel-processing low-power verdi cgra upf dvt uvm-verification uvm-testbench
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Apr 15, 2026 - SystemVerilog
UVM-based register verification environment using explicit predictor
systemverilog uvm testbench predictor uvm-ral-model uvm-register-model uvm-verification uvm-testbench designverification
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Mar 9, 2026 - SystemVerilog
A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router
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Sep 3, 2025 - JavaScript
Hands-on Design Verification — SystemVerilog testbenches, full UVM environment for APB Protocol, Python scripting, SVA assertions & functional coverage. Trained at ChipEdge using Synopsys VCS.
python-script verilog synopsis systemverilog sva design-verification functional-coverage uvm-testbench apb-protocol
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May 23, 2026 - SystemVerilog
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