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unsloth: pin #241 with the CUDA graph cache cap removal, repin Inkling and #61 onto b11529 - #257

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danielhanchen merged 4 commits into
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pin-241-fold-253
Oct 10, 2026
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danielhanchen merged 4 commits into
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pin-241-fold-253

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@danielhanchen danielhanchen commented Oct 9, 2026 •

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Pins #241 again in place of #253. The built tree does not change: both point at the same commit, 20dd977.

The 64-entry CUDA graph cache cap that #253 removes came from #241's own commit, ggml-cuda: key the CUDA graph cache by shape. So the fix belongs in #241:

feature-checks.json moves the unchecked entry back to #241, with the cap noted in its reason.

Verification

Inkling repin for b11515

Today's base, b11515, includes ggml-org#30147. That PR loops the CUDA PAD kernel over rows and slices past 65535 and rewrote the line Inkling's int64 dst_idx fix touches, so ggml-org#25731 stopped merging. Its branch now merges b11515 and keeps the casts inside the new loop. Upstream's version still computes the index in int.

#61 repin for b11517

b11517 brings ggml-org#30168. It makes the src1 precision an explicit template argument of the CUDA MMQ helpers and drops its GGML_PREC_Q8 default. #61 broke in three places:

  • the mmq.cuh switch cases, a text conflict;
  • the three IQ1 tile loaders, which merged cleanly but no longer compiled;
  • mul_mat_q_case in mmq.cu, which also merged cleanly but no longer compiled.

The CPU-only dry run cannot see the last two. #61 now merges b11517 and passes GGML_PREC_Q8 in all three places, the same value the default had and the same thing upstream does for IQ1_S. Its PR base moves to b11517 as well.

  • CUDA test-backend-ops, all passing:
    • MUL_MAT: 2483/2483 (39 iq1_x* cases, batch sizes up to 64);
    • MUL_MAT_ID: 940/940 (9 iq1_x* cases);
    • GET_ROWS: 216/216 (24 iq1_x* cases).
  • On b11517:
    • all 15 pins merge;
    • pin_contract.py: all intact;
    • merge_checks.py: clean;
    • the CPU gate build passes;
    • feature_matrix.py: 7/7 features.

Inkling repin for b11529

b11529 brings ggml-org#28636, which moves the ModelOpt FP8 dequant loop in conversion/base.py into a dequant_fp8() helper. Inkling's stacked-expert NVFP4 rejection sat in front of that loop and now sits in front of the call. Inkling's copy of the old loop was identical to the old upstream copy before the merge, so no behaviour is lost.

Results on b11529:

  • Merge, pin_contract.py and merge_checks.py: all 15 pins merge, all are intact, and the merged tree is clean. The same holds on b11517.
  • Converter: a tiny Qwen2 converts to a byte-identical GGUF on upstream b11529 and on the merged Inkling branch.
  • Build: the CPU gate and the full CUDA build both pass.
  • CUDA test-backend-ops: MUL_MAT 2483/2483, MUL_MAT_ID 940/940, PAD 37/37 and GET_ROWS 216/216.
  • feature_matrix.py --gpu on the CUDA build: all 7 features pass on GPU, including the checks CI skips (iq1 grids 3 x 13/13, glm5next 192/192, Inkling 13/13).

… removal

The 64 entry cap came from #241's own shape keyed graph cache commit, so the
fix belongs on #241. Its branch now includes #253's commit (same head,
20dd977), and the pin goes back to #241. The built tree is unchanged.
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📝 Code Review ✅ Completed 2026-10-09T12:15:14.549697Z 40ac0cb PR opened
🔒 Security Review ✅ Completed 2026-10-09T12:16:50.271808Z 40ac0cb PR opened
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b11515 brings ggml-org#30147, which loops the CUDA PAD kernel over rows and
slices past 65535. Inkling's int64 dst_idx fix touched the same line, so the
pin stopped merging. The Inkling branch now merges b11515 and keeps the cast
inside the new loop (test-backend-ops -o PAD: 37/37 on CUDA).
@danielhanchen danielhanchen changed the title unsloth: pin #241 again, now that it carries the CUDA graph cache cap removal unsloth: pin #241 with the CUDA graph cache cap removal, repin Inkling onto b11515 Oct 9, 2026
b11517 brings ggml-org#30168, which makes the src1 precision an explicit
argument of the CUDA MMQ helpers and drops its default. #61's three IQ1 types
now pass GGML_PREC_Q8 in the switch cases, the tile loaders and
mul_mat_q_case, as upstream does for IQ1_S (test-backend-ops MUL_MAT,
MUL_MAT_ID, GET_ROWS on CUDA all pass, incl. the MMQ batch sizes).
@danielhanchen danielhanchen changed the title unsloth: pin #241 with the CUDA graph cache cap removal, repin Inkling onto b11515 unsloth: pin #241 with the CUDA graph cache cap removal, repin Inkling and #61 onto b11517 Oct 9, 2026
b11529 brings ggml-org#28636, which moves the ModelOpt FP8 dequant loop in
conversion/base.py into a dequant_fp8() helper. Inkling's stacked-expert
NVFP4 rejection sat in front of that loop; it now sits in front of the call.
@danielhanchen danielhanchen changed the title unsloth: pin #241 with the CUDA graph cache cap removal, repin Inkling and #61 onto b11517 unsloth: pin #241 with the CUDA graph cache cap removal, repin Inkling and #61 onto b11529 Oct 9, 2026
@danielhanchen
danielhanchen merged commit 207fdee into master Oct 10, 2026
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