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vigneshsangaa/README.md

Sanga Vignesh

RTL Design Engineer  |  Digital & FPGA Enthusiast

Final-Year ECE Undergraduate @ RGUKT Basar  •  RTL  |  FPGA  |  Verification  |  Physical Design Verilog  •  SystemVerilog  •  STA  •  ASIC Design Flow




About Me

  • 🎓 Final-year B.Tech ECE student at RGUKT Basar, graduating 2027 — GPA 8.40/10
  • ⚙️ Focused on RTL Design, FPGA Implementation, and Static Timing Analysis
  • 🔬 Research Intern @ NIT Warangal — designed FIR filters & DCO blocks for an ADPLL in UMC 180nm
  • 🧠 Built a full RTL-to-GDSII flow for a UART core using Cadence tools (Genus, Innovus, Conformal)
  • ❤️ Designed CardioEdge, an FPGA-based real-time ECG arrhythmia classifier on Artix-7
  • 🧮 Designed a single-cycle RV32I RISC-V processor in Verilog, verified via self-checking testbench and Vivado synthesis/implementation
  • 📡 Exploring Verification (UVM) and Physical Design as I move toward full-stack digital design
  • 🏆 GATE 2026 (ECE) — AIR 3868, Score 528

Tech Stack

Hardware Description & Verification

EDA / Design Tools

Programming & Data

Machine Learning / Tools

Featured Projects

🫀 CardioEdge

Real-Time ECG Arrhythmia Detection on FPGA

Custom FSM-based control logic with pipelined Verilog datapath for real-time 5-class arrhythmia classification (1D-CNN, 82% accuracy). Closed timing at 71.43 MHz on Artix-7 with zero setup/hold violations.

Verilog Vivado PyTorch Artix-7

🔗 UART: RTL to GDSII

Full Digital Design Flow on SCL 180nm

Verilog RTL for a UART core, verified via self-checking testbench on Xcelium, RTL-netlist equivalence via Conformal, synthesized in Genus with 0 DRC violations and 8.275ns signoff slack.

Verilog Cadence Genus Xcelium

📡 ADPLL Research @ NIT Warangal

FIR Filter & DCO Design in UMC 180nm

25th-order FIR digital loop filter and 4-stage ring-oscillator DCO with ÷64 divider. Closed-loop ADPLL verified in Cadence Spectre — 8ns lock time, 2.26GHz output at 5.3mW.

Verilog-A Cadence Virtuoso Spectre

🧮 RV32I Single-Cycle RISC-V Processor

32-bit RISC-V Core in Verilog

Single-cycle RV32I processor implementing all 37 base instructions, verified with a self-checking testbench (350/350 checks passed across 104 instructions). Synthesized and implemented in Vivado targeting Artix-7 with all timing constraints met (WNS 0.779ns).

Verilog Vivado RISC-V Artix-7

Currently Learning

Achievements

Let's Connect

I'm actively looking for entry-level RTL Design / FPGA Design / Verification roles. Open to conversations about chips, silicon, or interesting problems.


Thanks for visiting my profile.

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  1. My-Portfolio My-Portfolio Public

    HTML 1

  2. AI-ML-Based-Digital-Loop-Filter-for-ADPLL AI-ML-Based-Digital-Loop-Filter-for-ADPLL Public

    An All-Digital PLL (UMC 180nm) with a 25th-order FIR digital loop filter whose coefficients are trained by an ANN — achieving 2.26 GHz output, 8 ns lock time, and 5.3 mW power.

    Jupyter Notebook 1

  3. uart-rtl2gds-scl180 uart-rtl2gds-scl180 Public

    Full RTL-to-GDS ASIC flow for a UART IP on SCL 180nm (Genus + Innovus). 293 cells, 42,910 µm², 32.2 µW, 0 DRC violations, 8.275 ns signoff slack - verified via RTL sim, GLS, and formal LEC.

    Verilog 1

  4. Edge_AI_Based_Arrhythmia_Detection_on_FPGA Edge_AI_Based_Arrhythmia_Detection_on_FPGA Public

    1D-CNN ECG arrhythmia classifier (5-class, MIT-BIH) trained in PyTorch, quantized to INT8, and deployed on Xilinx Artix-7 (xc7a35t) FPGA. ~82% accuracy,~60 KB model, runs upto 72 MHz with 0 failing…

    Jupyter Notebook 1

  5. RISC-V_Single_Cycle_Processor RISC-V_Single_Cycle_Processor Public

    32-bit single-cycle RV32I RISC-V processor in Verilog, verified via simulation and Vivado synthesis/implementation — all 37 base instructions tested.

    Verilog