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  • University of Technology and Engineering
  • 01 Vo Van Ngan Street, Linh Chieu Ward, Thu Duc District, Ho Chi Minh City, Vietnam
  • LinkedIn in/phamquanghop

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QuangHop-dev/README.md

"Give it a bit more effort - for the life you want, people you hope to meet, the person you aim to be."

— A meaningful quote here

Hi, I'm Lucas (Phạm Quang Hợp) 👋

📫 How to reach me: LinkedIn

-> [Main Subject]
-> [Projects & Labs]
-> [Online Courses]


Main Subjects

Here, these are the main subjects organized according to the Digital/Analog IC Design track in my curriculum.

Order Course Year Semester
1 C Programing Language 2022 Fall
2 Digital Systems 2023 Spring
3 Basic Electronic 2023 Fall
4 Data Communication 2023 Fall
5 Computer Architecture 2024 Spring
6 Digital Signal Processing 2024 Fall
7 FPGA/ASIC Digital System Design 2024 Spring
8 VLSI Intergrated Circuit Design (CMOS) 2025 Spring
9 Hardware/Software Codesign 2025 Spring

Projects & Labs

Topic Project Year
RTL Design
1 Implement_FFT_8point_on_FPGA 2023
2 Designing a simple 32-bit RISC-V processor 2025
3 Designing a APB2UART Bridge 2025
3 Designing of HW for Accelerating the Kyber PQC Algorithm 2026
Design Verification
4 Synchronous FIFO Design and Verification 2023
5 Verification of AXI Slave Memory using UVM 2026
6 UART Design and Verification using UVM 2025
Analog Circuit Design
7 1.6-GHz PLL design 2024
Custom IC Design and Layout
8 8x8 SRAM 6T array design and layout 2024

Online Courses by Udemy Platform

Course Year Semester
Verification series (1-7) focusing in-depth on SV/UVM by Kumar Khandagle 2026 Spring
ASIC Synthesis-STA-Physical Design(PD):Cadence+Synopsys flow 2025 Fall
VSD - Static Timing Analysis Series (1-2) by Kunal Ghosh 2026 Spring

Pinned Loading

  1. UART_AHB-slave_Design-and-Verification UART_AHB-slave_Design-and-Verification Public

    Performed verification with multiple test scenarios such as write/read operations, fill full FIFO, bad parity injection, baud rate configuration in directed and random tests on QuestaSim.

    SystemVerilog 1

  2. Design_and_Layout_of_an_8x8-SRAM-array Design_and_Layout_of_an_8x8-SRAM-array Public

    The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE.

    1

  3. Analog_Design_of_1.28-GHz_PLL_system Analog_Design_of_1.28-GHz_PLL_system Public

    This project shows the design of a frequency synthesizer PLL system that produces a 1.28 GHz signal with a reference input of 40 MHz.