Design_and_Layout_of_an_8x8-SRAM-array

The project is about building an 8-row by 8-bit SRAM memory array, using 45nm CMOS technology. Using a 3-to-8 decoder, the SRAM array is accessed by a 3-bit address. The test-bench, the implementation, and the layout of the SRAM array and the decoder are done using Cadence Virtuoso’s Analog-Design Environment (ADE).

System Block Diagram

6T SRAM array Design

1) Decoder 3-8

2) Pre-charge

3) Write-driver

4) Sense-amplifier

5) Cell-unit

Whole System Design and Layout

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References

• Abinaya. M, Devipriya S, Arul R, Devasenapathi C, "Comparative Analysis of 16 bit SRAM using various SRAM cells in 45nm CMOS technology", Journal of Information and Computational Science, vol. 9, no. 01/2019, pp. 123-133
• Kumar, P. V., Kumar, A., S., B., Ravika, G., & Sattigeri, S. K. (2021). “Design and implementation of 16Bit 6T SRAM using 45nm, 90nm, 180nm CMOS technology”. International Research Journal of Engineering and Technology (IRJET), 8(7), 2190
• Video on how to do layout on Cadence Virtuoso: https://www.youtube.com/watch?v=W5aglIZuel4