The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE.
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Updated
Mar 2, 2026
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custom-ic
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Transistor-level 6T Static RAM Bitcell Full Custom Layout in Magic VLSI with Transient Read/Write Stability Analysis.
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Updated
Aug 22, 2026
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