Digital IC & Microarchitecture Engineer | Aspiring Master's in Microelectronics & CompArch (Germany)
Focused on Processor Microarchitecture, RTL Design, Cache/Memory Subsystems, and Open-Source ASIC Implementation (SkyWater 130nm).
- Processor Microarchitecture: 5-Stage In-Order Pipelines, Dynamic Branch Prediction (BHT/BTB), Hazard Resolution, Out-of-Order Execution concepts (ROB, Reservation Stations, CDB).
- RTL & Hardware Design: SystemVerilog (IEEE 1800), Verilog-2001, Structural & Behavioural Modeling.
- Memory & Interconnect: L1 Cache Controllers (Direct-Mapped / Write-Back), SRAM Bitcell Layout, Memory-Mapped Peripherals (GPIO, UART, I2C, Timers).
- EDA & Physical Implementation: Yosys Open Synthesis, SkyWater 130nm PDK (
sky130A), Magic VLSI Layout, Ngspice, Xilinx Vivado. - Architectural Exploration: C-based Instruction-Level Simulators, Microarchitectural Tradeoff Analysis (Hennessy & Patterson Quantitative Approach).
| Category | Technologies & Tools |
|---|---|
| HDL & Languages | SystemVerilog, Verilog, C/C++, Python |
| Simulation & Verification | Icarus Verilog (iverilog), GTKWave, ModelSim, Vivado XSIM, Verilator |
| Synthesis & ASIC Flow | Yosys, OpenLane / OpenROAD, Sky130 PDK, Xilinx Vivado |
| Custom IC & Transistor | Magic VLSI, Ngspice |
| Architectures & ISAs | RISC-V (RV32I), MIPS-32 |
| Project / Ecosystem | Focus Area | Status / PR | Details |
|---|---|---|---|
| lowRISC/ibex | RISC-V Core RTL | Upstream PR | Verification & RTL parameterization exploration |
| lowRISC/opentitan | Silicon Root-of-Trust | Contributor | Open-source hardware tooling & IP validation |
- 🚀 M32_MCU_V1: 32-bit SoC integrating a pipelined CPU core with an on-chip peripheral subsystem (UART, I2C, Timers, GPIO) synthesized to Sky130 standard cells.
- ⚙️ Mips_32_processor: Evolutionary CPU architecture: Single-Cycle
$\rightarrow$ 5-Stage Pipeline with Forwarding/Stalls$\rightarrow$ 2-Bit Dynamic Branch Prediction$\rightarrow$ Tomasulo Out-of-Order Engine. - ⚡ DirectCache: Synthesizable direct-mapped L1 cache controller with tag comparison, valid/dirty bit tracking, and write-back/write-allocate FSM.
- 📐 6TSRAMBitcell: Custom IC layout of a 6T SRAM cell in Magic VLSI with transient stability analysis.
- 💻 ToyProcessor: Cycle-accurate, C-based instruction-level processor simulator for architectural exploration and disassembling.
- 💼 LinkedIn: linkedin.com/in/your-profile
- 🎯 Target: MS in Germany (Winter 2027) | Digital Design & RISC-V Architecture Opportunities