Direct-Mapped L1 Cache Subsystem

A synthesizable direct-mapped L1 cache memory controller designed to bridge high-speed processor execution pipelines with high-latency backing memory systems.

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⚙️ Cache Architecture & Addressing

The direct-mapped cache indexes memory blocks directly using field-decomposed address lines:

• Cache Organization: Direct-Mapped (1 line per set).
• Line / Block Size: 4 Bytes (32-bit word).
• Address Breakdown:
  • Tag (addr[5:3]): 3 bits for block identity matching against Tag RAM.
  • Index (addr[2:0]): 3 bits (8 cache lines / sets).
  • Offset: Word-aligned access.
• Write Policy: Write-Back (main memory updated only on dirty line eviction) with Write-Allocate on write misses.

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🏗️ Cache Controller Finite State Machine (FSM)

stateDiagram-v2
    [*] --> IDLE
    IDLE --> COMPARE_TAG: Memory Read/Write Request
    COMPARE_TAG --> IDLE: Cache Hit (Served in 0 stall cycles)
    COMPARE_TAG --> WRITE_BACK: Cache Miss & Dirty Bit Set
    COMPARE_TAG --> ALLOCATE: Cache Miss & Clean Line
    WRITE_BACK --> ALLOCATE: Main Memory Eviction Write Complete
    ALLOCATE --> COMPARE_TAG: Backing Memory Line Refill Complete

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🔄 Microarchitectural Operation

1. Tag Comparison & Hit Detection:
   • On access, ind = addr[2:0] indexes the cache set.
   • Hit is asserted if v[ind] == 1 (valid bit) and tag[ind] == addr[5:3].
2. Read / Write Hits:
   • Read hits output data immediately with zero stall bubbles (stl = 0).
   • Write hits update the line buffer and set the dirty bit (d[ind] = 1).
3. Miss Penalty & Write-Back:
   • If a miss occurs and the resident line is dirty, the controller stalls the core (stl = 1) and bursts the dirty word to main memory before allocating the requested block.

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📊 Technical Specifications

Parameter	Specification
Capacity	8 Lines x 4 Bytes (32 Bytes baseline model)
Associativity	Direct-Mapped (1-Way)
Hit Latency	1 Clock Cycle
Status Bits	1 Valid Bit + 1 Dirty Bit per cache line
Replacement Policy	Direct Set Overwrite with Dirty Flush

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🛠️ Simulation & Verification

# 1. Compile cache testbench
iverilog -o sim/cache_sim.vvp rtl/*.v tb/tb_cache.v

# 2. Run simulation
vvp sim/cache_sim.vvp

# 3. View waveforms in GTKWave
gtkwave sim/waveform.vcd