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[mlir][dxsa] Add control flow instructions#194

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tagolog wants to merge 4 commits into
dxsa-mlirfrom
vshiryaev/dxsa-mlir-control-flow-instructions
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[mlir][dxsa] Add control flow instructions#194
tagolog wants to merge 4 commits into
dxsa-mlirfrom
vshiryaev/dxsa-mlir-control-flow-instructions

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@tagolog

@tagolog tagolog commented Jun 21, 2026

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  • break
  • continue
  • default
  • else
  • endif
  • endloop
  • endswitch
  • loop
  • ret

Example:

  dxsa.break
  dxsa.continue
  dxsa.default
  dxsa.else
  dxsa.endif
  dxsa.endloop
  dxsa.endswitch
  dxsa.loop
  dxsa.ret

@tagolog tagolog requested review from asavonic, asl and hvdijk June 21, 2026 19:41
@tagolog tagolog self-assigned this Jun 21, 2026
@hvdijk

hvdijk commented Jun 22, 2026

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I suppose there is an open question here: do we want structured MLIR? If we do, we wouldn't model e.g. dxsa.endif as an instruction, we'd instead give dxsa.if a block and make the dxsa.endif implicit?

Comment thread mlir/lib/Target/DXSA/BinaryParser.cpp Outdated
@asl

asl commented Jun 22, 2026

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I suppose there is an open question here: do we want structured MLIR?

No. This is a bytecode dialect.

tagolog added 2 commits June 24, 2026 22:42
 - break
 - continue
 - default
 - else
 - endif
 - endloop
 - endswitch
 - loop
 - ret

Example:
  dxsa.break
  dxsa.continue
  dxsa.default
  dxsa.else
  dxsa.endif
  dxsa.endloop
  dxsa.endswitch
  dxsa.loop
  dxsa.ret

Signed-off-by: Vladimir Shiryaev <vshiryaev@accesssoftek.com>
…split-input-file`

Signed-off-by: Vladimir Shiryaev <vshiryaev@accesssoftek.com>
@tagolog tagolog force-pushed the vshiryaev/dxsa-mlir-control-flow-instructions branch from 1e72f2f to 0bdc78d Compare June 25, 2026 05:44
@tagolog tagolog requested a review from hvdijk June 25, 2026 05:46
// DXSA shared bases for ops with inline operands
//===----------------------------------------------------------------------===//

class DXSA_NullaryOp<string mnemonic> : DXSA_Op<mnemonic> {

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This name is inconsistent with the above description and below classes. It's used in this PR for ops without inline operands, when the above description says "ops with inline operands". UnaryOp means one source operand, one destination operand. BinaryOp means two source operands, one destination operand. TernaryOp means three source operands, one destination operand. NullaryOp, by extension, would mean zero source operands, one destination operand. But that means it isn't suitable for the instructions you're defining in this PR.

If we merge #201 first, we can avoid the need to create a NullaryOp by making a slight tweak to it to modify PlainOp to make $precise optional, and use PlainOp<"...", 0, 0, 0> or such.

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If we merge #201 first, we can avoid the need to create a NullaryOp by making a slight tweak to it to modify PlainOp to make $precise optional, and use PlainOp<"...", 0, 0, 0> or such.

As it turns out, we have many zero-argument instructions.
I think it will be still useful to have a synonym for PlainOp<..., 0, 0, 0> for declaring such instructions (in case we decide to replace PlainOp<..., 0, 0, 0> with something else, for some reason). Would it be ok to call it DXSA_ZeroOperandOp, as an alternative for DXSA_NullaryOp or DXSA_ZeroOp?

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Would it be ok to call it DXSA_ZeroOperandOp, as an alternative for DXSA_NullaryOp or DXSA_ZeroOp?

I think it still wouldn't belong here based on "ops with inline operands", but I'm now thinking it may be better to just update that description.

Looking at other instructions not yet covered, we also have instructions with source operands but no destination operands (mostly in #160, which needs updating). How would you feel about DXSA_NullaryOp<string mnemonic, int dsts = 1, bit hasprecise = 1> : DXSA_PlainOp<mnemonic, dsts, 0, hasprecise>;, and likewise for DXSA_UnaryOp, DXSA_BinaryOp, DXSA_TernaryOp ? That way, we can use DXSA_NullaryOp<"break", 0>, DXSA_UnaryOp<"breakc", 0>, etc. ?

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As discussed in the call I created a branch to show what this would look like with the approach from #201 (slightly different from what is currently in #201, which I will update), 347ef62

tagolog added 2 commits June 27, 2026 01:36
Signed-off-by: Vladimir Shiryaev <vshiryaev@accesssoftek.com>
- call
- callc
- case
- label
- abort
- debug_break

Example:

  dxsa.call
  dxsa.callc
  dxsa.case
  dxsa.label
  dxsa.abort
  dxsa.debug_break

Signed-off-by: Vladimir Shiryaev <vshiryaev@accesssoftek.com>
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4 participants