WIP: Preview for adding imxrt118x architecture

arch/arm/Kconfig

@@ -198,16 +198,14 @@ config ARCH_CHIP_IMX9_CORTEX_M
 
 config ARCH_CHIP_IMXRT
 	bool "NXP/Freescale iMX.RT"
-	select ARCH_CORTEXM7
 	select ARCH_HAVE_MPU
 	select ARCH_HAVE_RAMFUNCS
 	select ARCH_HAVE_TICKLESS
 	select ARCH_HAVE_I2CRESET
 	select ARCH_HAVE_SPI_CS_CONTROL
 	select ARM_HAVE_MPU_UNIFIED
-	select ARMV7M_HAVE_STACKCHECK
 	---help---
-		NXP i.MX RT (ARM Cortex-M7) architectures
+		NXP i.MX RT (ARM Cortex-M7 or Cortex-M33) architectures.
 
 config ARCH_CHIP_KINETIS
 	bool "NXP/Freescale Kinetis"

arch/arm/include/imxrt/chip.h

@@ -84,6 +84,11 @@
 /* MIMXRT1170DVMA TODO
  */
 #  define IMXRT_GPIO_NPORTS            13           /* Thirteen total ports */
+#elif defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33)
+/* MIMXRT1189CVM8C - Dual-core Cortex-M33 + Cortex-M7 */
+
+#  define IMXRT_GPIO_NPORTS            6            /* Six general purpose GPIO ports */
 #else
 #  error "Unknown i.MX RT chip type"
 #endif

arch/arm/include/imxrt/irq.h

@@ -42,6 +42,8 @@
 #  include <arch/imxrt/imxrt106x_irq.h>
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT117x)
 #  include <arch/imxrt/imxrt117x_irq.h>
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x)
+#  include <arch/imxrt/imxrt118x_irq.h>
 #else
 #  error Unrecognized i.MX RT architecture
 #endif

arch/arm/src/armv7-m/arm_fpuconfig.c

@@ -60,6 +60,16 @@ void arm_fpuconfig(void)
 {
   uint32_t regval;
 
+  /* Enable full access to CP10 and CP11 before setting CONTROL.FPCA (see
+   * ARMv7-M Architecture Reference Manual, DDI 0403E.e).  Otherwise cores
+   * which have the coprocessor disabled at reset will raise a NOCP usage
+   * fault.
+   */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
+  putreg32(regval, NVIC_CPACR);
+
   /* Set CONTROL.FPCA so that we always get the extended context frame
    * with the volatile FP registers stacked above the basic context.
    */
@@ -76,10 +86,4 @@ void arm_fpuconfig(void)
   regval = getreg32(NVIC_FPCCR);
   regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
   putreg32(regval, NVIC_FPCCR);
-
-  /* Enable full access to CP10 and CP11 */
-
-  regval = getreg32(NVIC_CPACR);
-  regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
-  putreg32(regval, NVIC_CPACR);
 }

arch/arm/src/imx9/imx9_edma.c

@@ -528,11 +528,11 @@
        * if not continue to free tcds in chain
        */
 
        next = dmach->flags & EDMA_CONFIG_LOOPDEST ?
               NULL : (struct imx9_edmatcd_s *)
               imx9_edma_dmaaddr_to_addr(tcd->dlastsga);
 
        imx9_tcd_free_nolock(tcd);
     }
 
   dmach->head = NULL;
@@ -548,12 +548,12 @@
   dmach->arg      = NULL;
   dmach->state    = IMX9_DMA_IDLE;
 
+  spin_unlock_irqrestore_nopreempt(&g_edma.lock, flags);
+
   if (callback)
     {
       callback((DMACH_HANDLE)dmach, arg, true, result);
     }
-
-  spin_unlock_irqrestore_nopreempt(&g_edma.lock, flags);
 }
 
 /****************************************************************************
@@ -1526,7 +1526,7 @@
 unsigned int imx9_dmach_idle(DMACH_HANDLE handle)
 {
   struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle;
   return dmach->state == IMX9_DMA_IDLE ? 0 : -1;
 }
 
 /****************************************************************************

arch/arm/src/imxrt/CMakeLists.txt

@@ -24,7 +24,11 @@
 
 # Required i.MX RT files
 
-set(SRCS imxrt_allocateheap.c imxrt_start.c imxrt_periphclks.c)
+set(SRCS imxrt_allocateheap.c imxrt_start.c)
+
+if(NOT CONFIG_IMXRT_RGPIO)
+  list(APPEND SRCS imxrt_periphclks.c)
+endif()
 
 if(CONFIG_IMXRT_PROGMEM)
   list(APPEND SRCS imxrt_flash.c)
@@ -35,23 +39,31 @@ list(
   SRCS
   imxrt_irq.c
   imxrt_clrpend.c
-  imxrt_gpio.c
-  imxrt_daisy.c
   imxrt_wdog.c
   imxrt_serial.c
   imxrt_xbar.c
   imxrt_ocotp.c
   imxrt_lowputc.c)
 
+if(CONFIG_IMXRT_RGPIO)
+  list(APPEND SRCS imxrt_rgpio.c)
+else()
+  list(APPEND SRCS imxrt_gpio.c imxrt_daisy.c)
+endif()
+
 # Configuration-dependent i.MX RT files
 
-if(CONFIG_IMXRT_CLOCKCONFIG_VER2)
+if(CONFIG_IMXRT_CLOCKCONFIG_VER3)
+  list(APPEND SRCS imxrt_clockconfig_ver3.c)
+elseif(CONFIG_IMXRT_CLOCKCONFIG_VER2)
   list(APPEND SRCS imxrt_clockconfig_ver2.c imxrt_pmu.c)
 else()
   list(APPEND SRCS imxrt_clockconfig_ver1.c)
 endif()
 
-if(CONFIG_IMXRT_IOMUX_VER2)
+if(CONFIG_IMXRT_IOMUX_VER3)
+  list(APPEND SRCS imxrt_iomuxc_ver3.c)
+elseif(CONFIG_IMXRT_IOMUX_VER2)
   list(APPEND SRCS imxrt_iomuxc_ver2.c)
 else()
   list(APPEND SRCS imxrt_iomuxc_ver1.c)
@@ -68,7 +80,11 @@ else()
 endif()
 
 if(CONFIG_IMXRT_GPIO_IRQ)
-  list(APPEND SRCS imxrt_gpioirq.c)
+  if(CONFIG_IMXRT_RGPIO)
+    list(APPEND SRCS imxrt_rgpioirq.c)
+  else()
+    list(APPEND SRCS imxrt_gpioirq.c)
+  endif()
 endif()
 
 if(CONFIG_ARM_MPU)
@@ -80,7 +96,11 @@ if(CONFIG_BUILD_PROTECTED)
 endif()
 
 if(CONFIG_IMXRT_EDMA)
-  list(APPEND SRCS imxrt_edma.c)
+  if(CONFIG_IMXRT_EDMA_VER3)
+    list(APPEND SRCS imxrt_edma_ver3.c)
+  else()
+    list(APPEND SRCS imxrt_edma.c)
+  endif()
 endif()
 
 if(CONFIG_IMXRT_USDHC)
@@ -149,4 +169,12 @@ if(CONFIG_IMXRT_ADC)
   endif()
 endif()
 
+if(CONFIG_IMXRT_ELE)
+  list(APPEND SRCS imxrt118x_ele.c)
+endif()
+
+if(CONFIG_IMXRT_TRDC)
+  list(APPEND SRCS imxrt118x_trdc.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/arm/src/imxrt/Kconfig

@@ -105,6 +105,33 @@ config ARCH_CHIP_MIMXRT1176DVMAA
 	select IMXRT_HAVE_USBOTG1
 	select IMXRT_HAVE_USBOTG2
 
+config ARCH_CHIP_MIMXRT1189CVM8C
+	bool "MIMXRT1189CVM8C (Cortex-M7 core)"
+	select ARCH_FAMILY_IMXRT118x
+	select ARCH_CORTEXM7
+	select ARCH_HAVE_DPFPU
+	select ARMV7M_HAVE_ICACHE
+	select ARMV7M_HAVE_DCACHE
+	select ARMV7M_HAVE_ITCM
+	select ARMV7M_HAVE_DTCM
+	select ARMV7M_HAVE_STACKCHECK
+	select ARMV7M_ITCM
+	select ARMV7M_DTCM
+	---help---
+		Target the Cortex-M7 core on the RT1189 SoC.
+
+config ARCH_CHIP_MIMXRT1189CVM8C_CM33
+	bool "MIMXRT1189CVM8C (Cortex-M33 core)"
+	select ARCH_FAMILY_IMXRT118x
+	select ARCH_CORTEXM33
+	select ARMV8M_HAVE_STACKCHECK
+	select IMXRT_ELE
+	select IMXRT_TRDC
+	---help---
+		Target the Cortex-M33 core on the RT1189 SoC.  Used to build a
+		NuttX bootloader / minimal application that runs on the M33 out
+		of reset.
+
 endchoice # i.MX RT Chip Selection
 
 # i.MX RT Families
@@ -126,12 +153,14 @@ config ARCH_FAMILY_MIMXRT1021C
 config ARCH_FAMILY_IMXRT102x
 	bool
 	default n
+	select ARCH_CORTEXM7
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ICACHE
 	select ARMV7M_HAVE_DCACHE
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
+	select ARMV7M_HAVE_STACKCHECK
 
 config ARCH_FAMILY_MIMXRT105xDVL6A
 	bool
@@ -150,12 +179,14 @@ config ARCH_FAMILY_MIMXRT105xCVL5A
 config ARCH_FAMILY_IMXRT105x
 	bool
 	default n
+	select ARCH_CORTEXM7
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ICACHE
 	select ARMV7M_HAVE_DCACHE
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
+	select ARMV7M_HAVE_STACKCHECK
 
 config ARCH_FAMILY_MXRT106xDVL6A
 	bool
@@ -174,12 +205,14 @@ config ARCH_FAMILY_MIMXRT106xCVL5A
 config ARCH_FAMILY_IMXRT117x
 	bool
 	default n
+	select ARCH_CORTEXM7
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ICACHE
 	select ARMV7M_HAVE_DCACHE
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
+	select ARMV7M_HAVE_STACKCHECK
 	select IMXRT_HIGHSPEED_GPIO
 	select IMXRT_HAVE_FLEXSPI2
 	select IMXRT_ADC_VER2
@@ -193,15 +226,32 @@ config ARCH_FAMILY_IMXRT117x
 	select IMXRT_FLEXCAN1_FD
 	select IMXRT_FLEXCAN2_FD
 
+config ARCH_FAMILY_IMXRT118x
+	bool
+	default n
+	select ARCH_HAVE_FPU
+	select IMXRT_HAVE_LPUART9
+	select IMXRT_HAVE_LPUART10
+	select IMXRT_HAVE_LPUART11
+	select IMXRT_HAVE_LPUART12
+	select IMXRT_IOMUX_VER3
+	select IMXRT_RGPIO
+	select IMXRT_CLOCKCONFIG_VER3
+	select IMXRT_EDMA_VER3
+	---help---
+		i.MX RT1180 dual-core Crossover Processors (Cortex-M33 + Cortex-M7).
+
 config ARCH_FAMILY_IMXRT106x
 	bool
 	default n
+	select ARCH_CORTEXM7
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU # REVISIT
 	select ARMV7M_HAVE_ICACHE
 	select ARMV7M_HAVE_DCACHE
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
+	select ARMV7M_HAVE_STACKCHECK
 	select IMXRT_HIGHSPEED_GPIO
 	select IMXRT_HAVE_FLEXSPI2
 	select IMXRT_HAVE_FLEXIO3
@@ -359,10 +409,73 @@ config IMXRT_CLOCKCONFIG_VER2
 	bool
 	default n
 
+config IMXRT_CLOCKCONFIG_VER3
+	bool
+	default n
+	---help---
+		Selects the RT118x-family clock configuration
+		(arch/arm/src/imxrt/imxrt_clockconfig_ver3.c).
+
 config IMXRT_IOMUX_VER2
 	bool
 	default n
 
+config IMXRT_IOMUX_VER3
+	bool
+	default n
+	---help---
+		Selects the "generation 3" IOMUXC driver used by RT118x.
+
+config IMXRT_RGPIO
+	bool
+	default n
+	---help---
+		Selects the RGPIO driver (arch/arm/src/imxrt/imxrt_rgpio.c) that
+		targets the RGPIO IP block used on RT118x.
+
+config IMXRT_ELE
+	bool
+	default n
+	---help---
+		Enable the NXP EdgeLock Enclave (ELE) messaging driver
+		(arch/arm/src/imxrt/imxrt118x_ele.c).  Present on RT118x-class
+		SoCs.
+
+config IMXRT_ELE_LOAD_FW
+	bool "Load ELE firmware from NuttX at boot"
+	depends on IMXRT_ELE
+	default n
+	---help---
+		Embed the ELE firmware AHAB container (CONFIG_IMXRT_ELE_FW_PATH)
+		in the NuttX image and hand it to the EdgeLock Enclave with a
+		LOAD_FW command early in imxrt118x_ele_init().
+
+		When disabled, the ELE firmware is instead packed as its own
+		AHAB container in the boot image, loaded by ROM code.
+
+config IMXRT_ELE_FW_PATH
+	string "ELE firmware AHAB container path"
+	depends on IMXRT_ELE
+	default "tools/imxrt1180/.cache/ele-fw/mxrt1180b0-ahab-container.img"
+	---help---
+		Path (relative to the NuttX top-level directory, or absolute) to
+		the NXP EdgeLock Enclave firmware AHAB container.
+
+config IMXRT_TRDC
+	bool
+	default n
+	---help---
+		Enable the Trusted Resource Domain Controller driver
+		(arch/arm/src/imxrt/imxrt118x_trdc.c).  Present on RT118x-class
+		SoCs.
+
+config IMXRT_EDMA_VER3
+	bool
+	default n
+	---help---
+		Selects the "generation 3" eDMA driver
+		(arch/arm/src/imxrt/imxrt_edma_ver3.c) used by RT118x.
+
 menu "i.MX RT Peripheral Selection"
 
 config IMXRT_EDMA
@@ -2350,6 +2463,7 @@ endmenu # i.MX RT Peripheral Selection
 menuconfig IMXRT_GPIO_IRQ
 	bool "GPIO Interrupt Support"
 	default n
+	depends on !IMXRT_RGPIO
 
 if IMXRT_GPIO_IRQ
 
@@ -2601,6 +2715,7 @@ endchoice # i.MX RT Boot Configuration
 
 choice
 	prompt "i.MX RT Primary RAM"
+	default IMXRT_TCM_PRIMARY if ARCH_CORTEXM33
 	default IMXRT_OCRAM_PRIMARY
 	---help---
 		The primary RAM is the RAM that contains the system BLOB's .data and
@@ -2618,6 +2733,13 @@ config IMXRT_SRAM_PRIMARY
 	bool "External SRAM primary"
 	depends on IMXRT_SEMC_SRAM
 
+config IMXRT_TCM_PRIMARY
+	bool "TCM primary"
+	---help---
+		Place the primary RAM in the core-local TCM (M7 DTCM or M33
+		System TCM, both aliased at IMXRT_DTCM_BASE).  The size is taken
+		from the linker script's _ram_size symbol.
+
 endchoice # i.MX RT Primary RAM
 
 menu "i.MX RT Heap Configuration"