arch/arm/am67: Add EPWM0/EPWM1 PWM lower-half driver - #20137
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Adds the AM67 GPIO lower half and a polled MCU_MCSPI0 master driver, with the pad configuration both need. The K3 instance is not the OMAP2 layout: an HL header block precedes the functional registers. Chip select is released only after CHSTAT.EOT, since a high SCLK otherwise drops it mid-word and truncates the write, and CHCTRL.EN stays asserted between transfers. t3-gem-o1 registers /dev/spi0 for its ICM-20948 (CS3) and LPS22DF (CS1), and raises NSH_MAXARGUMENTS to 16 so the spi tool can address a device. Verified on t3-gem-o1: WHO_AM_I reads 0xEA on CS3 and 0xB4 on CS1, and the ICM-20948 streams continuous accelerometer samples over the bus. Co-authored-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com> Assisted-by: Cursor Assisted-by: Claude Code:claude-opus-4-8 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Add a Peripheral Support section to the board page listing the GPIO and MCU_MCSPI0 drivers, and replace the "UART console only" warning on both the chip and board pages -- it no longer describes the port. The replacement states what actually constrains the port: NuttX runs on the R5F under RemoteProc and depends on the bootloader or Linux Device Manager having powered and clocked the peripherals, because there is no TISCI client yet. Assisted-by: Claude Code:claude-opus-5 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds an I2C master driver for the AM67 I2C instances, completing transfers on ARDY as the K3 controller signals. Bring-up is deferred to the first transfer, because the Linux Device Manager enables the I2C clocks late and touching the bus during early board init is not safe here. The last reference drop clears the flag so the next transfer re-initialises the hardware. t3-gem-o1 registers WKUP_I2C0 as /dev/i2c2. Verified on t3-gem-o1: i2c dev finds 0x30, 0x40, 0x51 and 0x68, the RTC at 0x68 reads a ticking BCD seconds register, repeated reads are consistent, and NACK recovery returns the bus to a usable state. Assisted-by: Claude Code:claude-fable-5 Assisted-by: Claude Code:claude-opus-4-8 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Record the WKUP_I2C0 master in the board's Peripheral Support list. Assisted-by: Claude Code:claude-opus-5 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds a PWM lower-half for EPWM0 and EPWM1, covering both output channels of each. The CTRL_MMR EPWM clock enables are unlocked once during board bring-up. t3-gem-o1 registers /dev/pwm0 and /dev/pwm1 with PWM_NCHANNELS=2. Verified on t3-gem-o1: all four outputs (EPWM0 A+B, EPWM1 A+B) drive physical pins, jumpered into a Linux GPIO input -- 50% and 20% duty read back at the expected sample ratios, and gpiomon timed a 50 Hz half-period at 9.998-10.002 ms. examples/pwm starts and stops a 1 kHz train cleanly. Assisted-by: Claude Code:claude-fable-5 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Record the EPWM0 and EPWM1 outputs in the board's Peripheral Support list. Assisted-by: Claude Code:claude-opus-5 Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
arch/arm/am67: Add EPWM0/EPWM1 PWM lower-half driver.
5 tasks
acassis
requested review from
JorgeGzm,
cederom,
linguini1,
raiden00pl,
simbit18 and
xiaoxiang781216
September 14, 2026 15:27
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Summary
output channels (EPWMxA and EPWMxB) of EPWM0 and EPWM1.
TBPRDand duty in
CMPA/CMPB, with the action-qualifier configured for standardedge-aligned output: set on zero, clear on compare.
before any instance is configured.
/dev/pwm0and EPWM1 as/dev/pwm1, withCONFIG_PWM_NCHANNELS=2so both channels are reachable through one device.Impact
Testing
Testing logs before change: no PWM support on this arch.
The version string in the logs is from the tested build; the commits were
GPG-signed afterwards, which rewrites hashes. The code is unchanged.
Testing logs after change:
Measured time base, captured 2026-09-11. The log above only shows the ioctl
returning; this reads the registers back from the A53 over
/dev/memwhileNuttX is driving the output.
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