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fix(trapezoid commutation): non-centred modulation produced no output for Uq < 0 #580

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fix(trapezoid commutation): non-centred modulation produced no output for Uq < 0 #580

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22 changes: 20 additions & 2 deletions src/BLDCMotor.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -165,7 +165,7 @@ void BLDCMotor::setPhaseVoltage(float Uq, float Ud, float angle_el) {
// centering the voltages around either
// modulation_centered == true > driver.voltage_limit/2
// modulation_centered == false > or Adaptable centering, all phases drawn to 0 when Uq=0
center = modulation_centered ? (driver->voltage_limit)/2 : Uq;
center = modulation_centered ? (driver->voltage_limit)/2 : 0;

if(trap_120_map[sector][0] == _HIGH_IMPEDANCE){
Ua= center;
Expand All @@ -184,6 +184,15 @@ void BLDCMotor::setPhaseVoltage(float Uq, float Ud, float angle_el) {
driver->setPhaseState(PhaseState::PHASE_ON, PhaseState::PHASE_ON, PhaseState::PHASE_OFF);// disable phase if possible
}

if(!modulation_centered){
// non-centered modulation: shift all phases up so the lowest one is at 0,
// same idiom as the sine/SVPWM branches
float Umin = min(Ua, min(Ub, Uc));
Ua -= Umin;
Ub -= Umin;
Uc -= Umin;
}

break;

case FOCModulationType::Trapezoid_150 :
Expand All @@ -193,7 +202,7 @@ void BLDCMotor::setPhaseVoltage(float Uq, float Ud, float angle_el) {
// centering the voltages around either
// modulation_centered == true > driver.voltage_limit/2
// modulation_centered == false > or Adaptable centering, all phases drawn to 0 when Uq=0
center = modulation_centered ? (driver->voltage_limit)/2 : Uq;
center = modulation_centered ? (driver->voltage_limit)/2 : 0;

if(trap_150_map[sector][0] == _HIGH_IMPEDANCE){
Ua= center;
Expand All @@ -217,6 +226,15 @@ void BLDCMotor::setPhaseVoltage(float Uq, float Ud, float angle_el) {
driver->setPhaseState(PhaseState::PHASE_ON, PhaseState::PHASE_ON, PhaseState::PHASE_ON); // enable all phases
}

if(!modulation_centered){
// non-centered modulation: shift all phases up so the lowest one is at 0,
// same idiom as the sine/SVPWM branches
float Umin = min(Ua, min(Ub, Uc));
Ua -= Umin;
Ub -= Umin;
Uc -= Umin;
}

break;

case FOCModulationType::SinePWM :
Expand Down