[deaneeth]

Summary

Phase 10: the engine synthesizes for the ECP5 LFE5U-85F (the ULX3S chip) and runs behind a UART.

• UART wrapper (fpga/ecp5/fpga_top.sv, uart.sv): CONFIG, LOAD, START and READ commands over 8N1; the reply carries the O words, cycles and byte counts.
• Simulated over the UART (bash sim/run_fpga.sh): FLASH causal and non-causal, and NAIVE. O is bit-exact against the golden model, and the cycle and byte counts match the models.
• Synthesis (bash fpga/ecp5/synth.sh, YoWASP Yosys and nextpnr): no latches, check -assert passes. 40,416 of 83,640 LUT4 positions, 8,726 flip-flops, 51 of 156 DSP blocks, no block RAM. fmax estimate 11.5 MHz, so timing is not closed at the 25 MHz board clock. No pin constraints.
• CI: fpga.yml runs the flow and writes the numbers to the job summary.
• RTL changes for Yosys (no behaviour change): packed LUT tables, file-scope package imports, local LUT copies before indexing, explicit sign extension in exp2_unit, and a split async reset in perf_counters. The unit suites, the 200-seed end-to-end sweep and the golden tests were rerun on them.
• Sim runners set CFG_CXXFLAGS_PCH_I=-include, because the installed Verilator leaves it empty and some models fail to link. See ARCHITECTURE section 15.

Verification

• bash sim/run_unit.sh: all suites passed.
• SEEDS=200 bash sim/run_e2e.sh: 3/3 passed.
• bash sim/run_fpga.sh: 1/1 passed.
• pytest sim/golden: passed.
• bash wasm/build.sh && node wasm/test.mjs: passed (the committed tiny_attn.wasm is rebuilt from this RTL).
• bash sim/lint.sh: clean.
• Web: pnpm lint, pnpm typecheck, pnpm build, pnpm test:e2e (35): passed.

Not done

• ULX3S pin constraints, a board run, timing closure at 25 MHz, and block RAM for the memories (the memories have combinational reads, so they map to LUT RAM).