SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.
python tcl rtl scoreboard sram regression-testing systemverilog modelsim testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project
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Updated
Apr 26, 2026 - SystemVerilog