RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
Simulation and implementation flow for hardware description languages
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol
全國大學校院積體電路設計競賽 實作練習
RISC-V Network Telemetry & Secure Packet Monitoring SoC-RTL design, AXI/AHB-Lite interconnects, hardware AES-128, packet telemetry, and verification using Synopsys VCS/Verdi.
APB based SPI master protocol
UVM verification of an APB-to-SPI master core: APB and SPI agents, virtual sequences for all 4 SPI modes, end-to-end scoreboard, SVA, 95.45% functional coverage
3x3 Q4.4 fixed-point matrix multiplier designed in Verilog and verified using Synopsys VCS and DVE.
32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.
Designed a lightweight 3-stage RISC-V processor for anomaly detection applications using Verilog, with RTL verification, synthesis, floorplanning, placement, CTS, routing, and STA using Synopsys VCS, Design Compiler, and ICC2.
complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys
A near-data accelerator SoC built around the VeeR EL2 RISC-V core, with a custom AXI4 interconnect and UART/GPIO/Timer peripherals.
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