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arch/arm/am67: Add I2C0/WKUP_I2C0 master driver - #20136

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t3gemstone:am67-pr-04
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t3gemstone:am67-pr-04

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Opening as draft since this depends on #20116 will mark ready once that lands.

Summary

  • Adds an I2C master driver for the AM67 I2C instances, following the TI flow:
    a transfer completes on ARDY rather than on the data-ready bits alone,
    which is what the K3 controller actually signals.
  • Bring-up is lazy. The controller is initialised on the first transfer rather
    than in am67_i2cbus_initialize(), because the Linux Device Manager enables
    the I2C clocks late and touching the bus during early board init is not safe
    on this part.
  • am67_i2cbus_uninitialize() clears the initialised flag when the last
    reference goes away, so the next transfer brings the hardware up again
    rather than talking to a torn-down controller.
  • t3-gem-o1 registers WKUP_I2C0 as /dev/i2c2; MAIN I2C0 is wired but not
    populated on this board.

Impact

  • Is new feature added? YES — I2C support for AM67.
  • Impact on user? NO — new driver, opt-in by Kconfig.
  • Impact on build? NO.
  • Impact on hardware? YES — arch/arm/am67 and board t3-gem-o1.
  • Impact on documentation? YES — provided in this PR (second commit).
  • Impact on security? NO.
  • Impact on compatibility? NO — additive.
  • Anything else? Depends on PR 3.

Testing

Build Host(s): Pardus GNU/Linux 25 (Debian 13 base), x86_64, host gcc 14
Toolchain:     arm-none-eabi-gcc 14.2.1 20241119 (15:14.2.rel1-1)
Target:        arm / TI AM67 (J722S) Cortex-R5F, board t3-gem-o1:nsh
nuttx-apps:    5a7ab4200
Loaded on the main-domain R5F by Linux remoteproc; console on UART-MAIN1.

Testing logs before change: no I2C support on this arch.

The version string in the logs is from the tested build; the commits were
GPG-signed afterwards, which rewrites hashes. The code is unchanged.

Testing logs after change:

make distclean && ./tools/configure.sh t3-gem-o1:nsh && make -j
  -> nuttx ELF 534980 bytes, 0 compiler warnings

Console:
nsh> i2c dev -b 2 0x03 0x77
NOTE: Some devices may not appear with this scan.
nsh> i2c get -b 2 -a 0x40 -r 0x00
READ Bus: 2 Addr: 40 Subaddr: 00 Value: 5a
nsh> i2c get -b 2 -a 0x40 -r 0x00
READ Bus: 2 Addr: 40 Subaddr: 00 Value: 5a
nsh> i2c get -b 2 -a 0x40 -r 0x00
READ Bus: 2 Addr: 40 Subaddr: 00 Value: 5a
nsh> i2c get -b 2 -a 0x40 -r 0x00
READ Bus: 2 Addr: 40 Subaddr: 00 Value: 5a
nsh> i2c get -b 2 -a 0x40 -r 0x00
READ Bus: 2 Addr: 40 Subaddr: 00 Value: 5a
nsh> i2c get -b 2 -a 0x40 -r 0x00
READ Bus: 2 Addr: 40 Subaddr: 00 Value: 5a
nsh>

Test plan result:
console_alive            PASS  prompt responsive
version                  PASS  NuttX version 0.0.0 218de36161 Sep 10 2026 13:48:24 t3-gem-o1:nsh
procfs                   PASS  procfs readable
tasks                    PASS  2 task lines
dev_nodes                PASS  all expected nodes present
i2c_scan                 PASS  found 0x30, 0x40, 0x51, 0x68
i2c_read                 PASS  0x5a
i2c_repeat               PASS  5/5 consistent reads

PASS=8
  i2c dev -b 2 0x03 0x77  -> 0x30, 0x40, 0x51, 0x68
  i2c get -b 2 -a 0x40 -r 0x00 x5 -> 0x5a each time (lazy re-init verified)

RTC read, captured 2026-09-11. The scan shows a device ACKing its address
and the reads above show transfers completing; this shows the bus carrying
data that changes.

nsh> i2c get -b 2 -a 0x68 -r 0x00
READ Bus: 2 Addr: 68 Subaddr: 00 Value: 36
nsh> sleep 3
nsh> i2c get -b 2 -a 0x68 -r 0x00
READ Bus: 2 Addr: 68 Subaddr: 00 Value: 39
nsh> sleep 3
nsh> i2c get -b 2 -a 0x68 -r 0x00
READ Bus: 2 Addr: 68 Subaddr: 00 Value: 43

The seconds register advances 36 -> 39 -> 43 across two 3 s waits.  The
step 39 -> 43 is a BCD carry rather than 0x3D, which confirms the byte is
BCD and not a raw counter.  The board has no backup cell, so the RTC
restarts from zero at power-up and only the tick is meaningful.

PR verification Self-Check

  • This PR introduces only one functional change.
  • I have updated all required description fields above.
  • My PR adheres to Contributing Guidelines and Documentation.
  • My PR is still work in progress (not ready for review).
  • My PR is ready for review and can be safely merged into a codebase.

halak0013 and others added 5 commits September 10, 2026 15:43
Adds the AM67 GPIO lower half and a polled MCU_MCSPI0 master driver, with the
pad configuration both need.  The K3 instance is not the OMAP2 layout: an HL
header block precedes the functional registers.

Chip select is released only after CHSTAT.EOT, since a high SCLK otherwise
drops it mid-word and truncates the write, and CHCTRL.EN stays asserted between
transfers.

t3-gem-o1 registers /dev/spi0 for its ICM-20948 (CS3) and LPS22DF (CS1), and
raises NSH_MAXARGUMENTS to 16 so the spi tool can address a device.

Verified on t3-gem-o1: WHO_AM_I reads 0xEA on CS3 and 0xB4 on CS1, and the
ICM-20948 streams continuous accelerometer samples over the bus.

Co-authored-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Assisted-by: Cursor
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Add a Peripheral Support section to the board page listing the GPIO and
MCU_MCSPI0 drivers, and replace the "UART console only" warning on both
the chip and board pages -- it no longer describes the port.  The
replacement states what actually constrains the port: NuttX runs on the
R5F under RemoteProc and depends on the bootloader or Linux Device
Manager having powered and clocked the peripherals, because there is no
TISCI client yet.

Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds an I2C master driver for the AM67 I2C instances, completing transfers on
ARDY as the K3 controller signals.

Bring-up is deferred to the first transfer, because the Linux Device Manager
enables the I2C clocks late and touching the bus during early board init is not
safe here.  The last reference drop clears the flag so the next transfer
re-initialises the hardware.

t3-gem-o1 registers WKUP_I2C0 as /dev/i2c2.

Verified on t3-gem-o1: i2c dev finds 0x30, 0x40, 0x51 and 0x68, the RTC at
0x68 reads a ticking BCD seconds register, repeated reads are consistent, and
NACK recovery returns the bus to a usable state.

Assisted-by: Claude Code:claude-fable-5
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Record the WKUP_I2C0 master in the board's Peripheral Support list.

Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
arch/arm/am67: Add I2C0/WKUP_I2C0 master driver.
@github-actions github-actions Bot added Area: Documentation Improvements or additions to documentation Arch: arm Issues related to ARM (32-bit) architecture Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. Board: arm labels Sep 14, 2026
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MemBrowse Memory Report

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Labels

Arch: arm Issues related to ARM (32-bit) architecture Area: Documentation Improvements or additions to documentation Board: arm Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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3 participants